Research Profile

Jean-Pierre Colinge

Biography

Current Director of TCAD Division, TSMC, Taiwan and has been in place since 2012. Professor Colinge can be contacted at jpcolinge@yahoo.com.

Research Grants

 ProjectFunding
Body
Start DateEnd DateAward
Semiconductor Nanowire Transistors SENATORScience Foundation of Ireland01-JAN-1131-DEC-15€2,398,720.00
Ultimate Integration on Silicon (ULIS)Science Foundation of Ireland01-SEP-1031-AUG-11€6,000.00
Junctionless Transistor SimulationsForeign Industry01-SEP-1031-DEC-15€112,500.00
SFI 04/W4/I634Science Foundation of Ireland01-JUL-0530-SEP-05€35,500.00

Publications

Books

 YearPublication
(2011)Semiconductor-on-insulator materials for nanoelectronics applications.
Nazarov, Alexei N and Colinge, JP and Balestra, Francis and Raskin, Jean-Pierre and Gamiz, Francisco and Lysenko, VS (2011) Semiconductor-on-insulator materials for nanoelectronics applications. : Springer. [Details]
(2009)Selected Papers from the EUROSOI'08 Conference.
Lederer, Dimitri and Colinge, Jean-Pierre (2009) Selected Papers from the EUROSOI'08 Conference. : Elsevier Limited. [Details]
(1995)Physical and technical problems of SOI structures and devices.
Colinge, Jean-Pierre and Lysenko, Vladimir S and Nazarov, Alexei N (1995) Physical and technical problems of SOI structures and devices. : Kluwer Academic Pub. [Details]
(2004)Silicon-on-insulator technology: materials to VLSI.
Colinge, Jean-Pierre and Colinge, J (2004) Silicon-on-insulator technology: materials to VLSI. : Springer. [Details]
(2005)Physics of semiconductor devices.
Colinge, J-P and Colinge, Cynthia A (2005) Physics of semiconductor devices. : Springer. [Details]
(2007)FinFETs and other multi-gate transistors.
Colinge, J-P (2007) FinFETs and other multi-gate transistors. : Springer. [Details]
(1996)Physique des dispositifs semi-conducteurs.
Colinge, Jean-Pierre and Van de Wiele, Fernand (1996) Physique des dispositifs semi-conducteurs. : De Boeck. [Details]

Book Chapters

 YearPublication
(2011)'Junctionless transistors: physics and properties'
Colinge, JP and Lee, CW and Akhavan, N Dehdashti and Yan, R and Ferain, I and Razavi, P and Kranti, A and Yu, R (2011) 'Junctionless transistors: physics and properties' In: Springer. [Details]
(2004)'The Soi Mosfet in a Harsh Environment'
Colinge, Jean-Pierre (2004) 'The Soi Mosfet in a Harsh Environment' In: Springer. [Details]
(2007)'MuGFET CMOS process with midgap gate material'
Xiong, W and Cleavelin, CR and Schulz, T and Schr\"ufer, K and Patruno, P and Colinge, Jean-Pierre (2007) 'MuGFET CMOS process with midgap gate material' In: Springer. [Details]
(2007)'Nanowire Quantum Effects in Trigate SOI MOSFETs'
Colinge, Jean-Pierre (2007) 'Nanowire Quantum Effects in Trigate SOI MOSFETs' In: Springer. [Details]
(2000)'SOI CMOS for high-temperature applications'
Colinge, JP (2000) 'SOI CMOS for high-temperature applications' In: Springer. [Details]
(2004)'Silicon-on-insulator and porous silicon'
Colinge, J-P (2004) 'Silicon-on-insulator and porous silicon' In: Springer. [Details]
(2004)'The soi mosfet'
Colinge, Jean-Pierre (2004) 'The soi mosfet' In: Springer. [Details]
(1997)'Soi Materials'
Colinge, Jean-Pierre (1997) 'Soi Materials' In: Springer. [Details]
(2000)'Recombination Current in Fully-Depleted SOI DIODES: Compact Model and Lifetime Extraction'
Ernst, T and Vandooren, A and Cristoloveanu, S and Rudenko, TE and Colinge, JP (2000) 'Recombination Current in Fully-Depleted SOI DIODES: Compact Model and Lifetime Extraction' In: Springer. [Details]
(1995)'SOI devices and circuits: an overview of potentials and problems'
Colinge, Jean-Pierre (1995) 'SOI devices and circuits: an overview of potentials and problems' In: Springer. [Details]
(2002)'Gate-All-Around technology for harsh environment applications'
Colinge, Jean-Pierre (2002) 'Gate-All-Around technology for harsh environment applications' In: Springer. [Details]
(1999)'RF Modelling and characterisation of SOI and bulk MOSFET’s'
Gillon, R and Vanhoenacker, D and Colinge, J-P (1999) 'RF Modelling and characterisation of SOI and bulk MOSFET’s' In: Springer. [Details]
(2004)'SOI CMOS Technology'
Colinge, Jean-Pierre (2004) 'SOI CMOS Technology' In: Springer. [Details]
(2007)'Doping Fluctuation Effects in Multiple-Gate SOI MOSFETs'
Colinge, CA and Xiong, W and Cleavelin, CR and Colinge, Jean-Pierre (2007) 'Doping Fluctuation Effects in Multiple-Gate SOI MOSFETs' In: Springer. [Details]
(1997)'Other SOI Devices'
Colinge, Jean-Pierre (1997) 'Other SOI Devices' In: Springer. [Details]
(2004)'Basics of Silicon-on-Insulator (SOI) Technology'
Colinge, J-P (2004) 'Basics of Silicon-on-Insulator (SOI) Technology' In: Springer. [Details]
(1997)'SOI Circuits'
Colinge, Jean-Pierre (1997) 'SOI Circuits' In: Springer. [Details]
(1995)'Novel TESC Bipolar Transistor Approach for a Thin-Film Silicon-On-Insulator Substrate'
Patel, CJ and Jankovic, ND and Colinge, JP (1995) 'Novel TESC Bipolar Transistor Approach for a Thin-Film Silicon-On-Insulator Substrate' In: Springer. [Details]
(2004)'SOI Materials Characterization'
Colinge, Jean-Pierre (2004) 'SOI Materials Characterization' In: Springer. [Details]
(1997)'The SOI MOSFET Operating in a Harsh Environment'
Colinge, Jean-Pierre (1997) 'The SOI MOSFET Operating in a Harsh Environment' In: Springer. [Details]
(2005)'On the Evolution of SOI Materials and Devices'
Colinge, Jean-Pierre (2005) 'On the Evolution of SOI Materials and Devices' In: Springer. [Details]
(2011)'Gate Modulated Resonant Tunneling Transistor (RT-FET): Performance Investigation of a Steep Slope, High On-Current Device Through 3D Non-Equilibrium Green Function Simulations'
Afzalian, Aryan and Colinge, Jean-Pierre and Flandre, Denis (2011) 'Gate Modulated Resonant Tunneling Transistor (RT-FET): Performance Investigation of a Steep Slope, High On-Current Device Through 3D Non-Equilibrium Green Function Simulations' In: Springer. [Details]
(2008)'The SOI MOSFET: From single gate to multigate'
Colinge, Jean-Pierre (2008) 'The SOI MOSFET: From single gate to multigate' In: Springer. [Details]

Peer Reviewed Journals

 YearPublication
(2011)'Nanowire to Single-Electron Transistor Transition in Trigate SOI MOSFETs'
Akhavan, N. D.,Afzalian, A.,Lee, C. W.,Yan, R.,Ferain, I.,Razavi, P.,Yu, R.,Fagas, G.,Colinge, J. P. (2011) 'Nanowire to Single-Electron Transistor Transition in Trigate SOI MOSFETs'. Ieee Transactions on Electron Devices, 58 (11):26-32   [Details]
(2010)'Simulation of junctionless Si nanowire transistors with 3 nm gate length'
Ansari, Lida,Feldman, Baruch,Fagas, Giorgos,Colinge, Jean-Pierre,Greer, James C. (2010) 'Simulation of junctionless Si nanowire transistors with 3 nm gate length'. Applied Physics Letters, 97 [Details]
(2010)'Effect of intravalley acoustic phonon scattering on quantum transport in multigate silicon nanowire metal-oxide-semiconductor field-effect transistors'
Akhavan, Nima Dehdashti,Afzalian, Aryan,Lee, Chi-Woo,Yan, Ran,Ferain, Isabelle,Razavi, Pedram,Yu, Ran,Fagas, Giorgos,Colinge, Jean-Pierre (2010) 'Effect of intravalley acoustic phonon scattering on quantum transport in multigate silicon nanowire metal-oxide-semiconductor field-effect transistors'. Journal of Applied Physics, 108 [Details]
(2010)'Simulation of Quantum Current Oscillations in Trigate SOI MOSFETs'
Akhavan, Nima Dehdashti,Afzalian, Aryan,Lee, Chi-Woo,Yan, Ran,Ferain, Isabelle,Razavi, Pedram,Fagas, Giorgos,Colinge, Jean-Pierre (2010) 'Simulation of Quantum Current Oscillations in Trigate SOI MOSFETs'. Ieee Transactions on Electron Devices, 57 [Details]
(2012)'Influence of channel material properties on performance of nanowire transistors'
Razavi, Pedram,Fagas, Giorgos,Ferain, Isabelle,Yu, Ran,Das, Samaresh,Colinge, Jean-Pierre (2012) 'Influence of channel material properties on performance of nanowire transistors'. Journal of Applied Physics, 111 [Details]
(2006)'Temperature effects on trigate SOI MOSFETs'
Colinge, J and Floyd, Liam and Quinn, Aidan J and Redmond, Gareth and Alderman, John C and Xiong, W and Cleavelin, C Rinn and Schulz, T and Schruefer, Klaus and Knoblinger, Gerhard and others (2006) 'Temperature effects on trigate SOI MOSFETs'. Electron Device Letters, IEEE, 27 (3):172-174 [Details]
(2012)'Resist-substrate interface tailoring for generating high density arrays of Ge and Bi2Se3 nanowires by electron beam lithography'
Hobbs, R. G.; Schmidt, M.; Bolger, C. T.; Georgiev, Y. M.; Xiu, F.; Wang, K. L.; Fleming, P.; Morris, M. A.; Djara, V.; Yu, R.; Colinge, J.-P.; Petkov, N.; Holmes, J. D. (2012) 'Resist-substrate interface tailoring for generating high density arrays of Ge and Bi2Se3 nanowires by electron beam lithography'. Journal of Vacuum Science & Technology B, 30 :041602(1)-041602(7)   [Details]
(2009)'Device characteristics of Trigate-FET with barrier constrictions in the channel'
Dehdashti, N.,Afzalian, A.,Lee, C. W.,Yan, R.,Fagas, G.,Colinge, J. P. (2009) 'Device characteristics of Trigate-FET with barrier constrictions in the channel'. Iwce-13: 2009 13th International Workshop on Computational Electronics, :246-249   [Details]
(2012)'Subthreshold behavior of junctionless silicon nanowire transistors from atomic scale simulations'
Ansari, L,Feldman, B,Fagas, G,Colinge, JP,Greer, JC (2012) 'Subthreshold behavior of junctionless silicon nanowire transistors from atomic scale simulations'. Solid-State Electronics, :58-62 [DOI] [Details]
(2006)'Low-temperature electron mobility in trigate SOI MOSFETs'
Colinge, J and Quinn, Aidan J and Floyd, Liam and Redmond, Gareth and Alderman, John C and Xiong, Weize and Cleavelin, C Rinn and Schulz, Thomas and Schruefer, Klaus and Knoblinger, Gerhard and others (2006) 'Low-temperature electron mobility in trigate SOI MOSFETs'. Electron Device Letters, IEEE, 27 (2):120-122 [Details]
(2012)'A Proposed Confinement Modulated Gap Nanowire Transistor Based on a Metal (Tin)'
Ansari, Lida,Fagas, Giorgos,Colinge, Jean-Pierre,Greer, James C. (2012) 'A Proposed Confinement Modulated Gap Nanowire Transistor Based on a Metal (Tin)'. Nano Letters, 12 [Details]
(2011)'Characterization of a junctionless diode'
Yu, R., Ferain, I., Akhavan, N.D., Razavi, P., Duffy, R., Colinge, J.-P. (2011) 'Characterization of a junctionless diode'. Applied Physics Letters, 99 (1)   [Details]
(2013)'Impact ionization induced dynamic floating body effect in junctionless transistors'
Yu, R., Nazarov, A.N., Lysenko, V.S., Das, S., Ferain, I., Razavi, P., Shayesteh, M., Kranti, A., Duffy, R., Colinge, J.-P. (2013) 'Impact ionization induced dynamic floating body effect in junctionless transistors'. Solid-State Electronics, 90 :28-33   [Details]
(2012)'Device design and estimated performance for p-type junctionless transistors on bulk germanium substrates'
Yu, R., Das, S., Ferain, I., Razavi, P., Shayesteh, M., Kranti, A., Duffy, R., Colinge, J.-P. (2012) 'Device design and estimated performance for p-type junctionless transistors on bulk germanium substrates'. IEEE Transactions on Electron Devices, 59 (9):2308-2313   [Details]
(2007)'Multi-gate SOI MOSFETs'
Colinge, JP (2007) 'Multi-gate SOI MOSFETs'. Microelectronic Engineering, 84 :2071-2076 [DOI] [Details]
(2010)'Variable temperature characterization of low-dimensional effects in tri-gate SOI MOSFETs'
Barrett, C and Lederer, D and Redmond, G and Xiong, W and Colinge, JP and Quinn, AJ (2010) 'Variable temperature characterization of low-dimensional effects in tri-gate SOI MOSFETs'. Solid-State Electronics, 54 (11):1273-1277 [Details]
(2006)'LETTERS-Silicon and Elemental Semiconductor Devices-Temperature Effects on Trigate SOI MOSFETs'
Colinge, JP and Floyd, L and Quinn, AJ and Redmond, G and Alderman, JC and Xiong, W and Cleavelin, CR and Schulz, T and Schruefer, K and Knoblinger, G and others (2006) 'LETTERS-Silicon and Elemental Semiconductor Devices-Temperature Effects on Trigate SOI MOSFETs'. IEEE Electron Device Letters, 27 (3):172-174 [Details]
(2010)'Nanowire transistors without junctions'
Colinge, Jean-Pierre and Lee, Chi-Woo and Afzalian, Aryan and Akhavan, Nima Dehdashti and Yan, Ran and Ferain, Isabelle and Razavi, Pedram and O'Neill, Brendan and Blake, Alan and White, Mary and others (2010) 'Nanowire transistors without junctions'. Nature nanotechnology, 5 (3):225-229 [Details]
(2004)'Multiple-gate soi mosfets'
Colinge, Jean-Pierre (2004) 'Multiple-gate soi mosfets'. Solid-State Electronics, 48 (6):897-905 [Details]
(2002)'Multiple-gate SOI MOSFETs: device design guidelines'
Park, Jong-Tae and Colinge, J (2002) 'Multiple-gate SOI MOSFETs: device design guidelines'. Electron Devices, IEEE Transactions on, 49 (12):2222-2229 [Details]
(2009)'Junctionless multigate field-effect transistor'
Lee, Chi-Woo and Afzalian, Aryan and Akhavan, Nima Dehdashti and Yan, Ran and Ferain, Isabelle and Colinge, Jean-Pierre (2009) 'Junctionless multigate field-effect transistor'. Applied Physics Letters, 94 (5) [Details]
(2001)'Pi-gate soi mosfet'
Park, Jong-Tae and Colinge, J and Diaz, Carlos H (2001) 'Pi-gate soi mosfet'. Electron Device Letters, IEEE, 22 (8):405-406 [Details]
(1997)'Substrate crosstalk reduction using SOI technology'
Raskin, J-P and Viviani, Alberto and Flandre, Denis and Colinge, J (1997) 'Substrate crosstalk reduction using SOI technology'. Electron Devices, IEEE Transactions on, 44 (12):2252-2261 [Details]
(1986)'Subthreshold slope of thin-film SOI MOSFET's'
Colinge, J (1986) 'Subthreshold slope of thin-film SOI MOSFET's'. Electron Device Letters, IEEE, 7 (4):244-246 [Details]
(1988)'Reduction of kink effect in thin-film SOI MOSFETs'
Colinge, J (1988) 'Reduction of kink effect in thin-film SOI MOSFETs'. Electron Device Letters, IEEE, 9 (2):97-99 [Details]
(1987)'An SOI voltage-controlled bipolar-MOS device'
Colinge, J (1987) 'An SOI voltage-controlled bipolar-MOS device'. Electron Devices, IEEE Transactions on, 34 (4):845-849 [Details]
(2010)'Performance estimation of junctionless multigate transistors'
Lee, Chi-Woo and Ferain, Isabelle and Afzalian, Aryan and Yan, Ran and Akhavan, Nima Dehdashti and Razavi, Pedram and Colinge, Jean-Pierre (2010) 'Performance estimation of junctionless multigate transistors'. Solid-State Electronics, 54 (2):97-103 [Details]
(2011)'Multigate transistors as the future of classical metal-oxide-semiconductor field-effect transistors'
Ferain, Isabelle and Colinge, Cynthia A and Colinge, Jean-Pierre (2011) 'Multigate transistors as the future of classical metal-oxide-semiconductor field-effect transistors'. Nature, 479 (7373):310-316 [Details]
(2010)'High-temperature performance of silicon junctionless MOSFETs'
Lee, Chi-Woo and Borne, Adrien and Ferain, Isabelle and Afzalian, Aryan and Yan, Ran and Akhavan, N Dehdashti and Razavi, Pedram and Colinge, J (2010) 'High-temperature performance of silicon junctionless MOSFETs'. Electron Devices, IEEE Transactions on, 57 (3):620-625 [Details]
(1997)'Comparison of TiSi2, CoSi2, and NiSi for Thin-Film Silicon-on-Insulator Applications'
Chen, J and Colinge, J-P and Flandre, Denis and Gillon, R and Raskin, Jean-Pierre and Vanhoenacker, D (1997) 'Comparison of TiSi2, CoSi2, and NiSi for Thin-Film Silicon-on-Insulator Applications'. Journal of The Electrochemical Society, 144 (7):2437-2442 [Details]
(1982)'Use of selective annealing for growing very large grain silicon on insulator films'
Colinge, JP and Demoulin, E and Bensahel, D and Auvert, G (1982) 'Use of selective annealing for growing very large grain silicon on insulator films'. Applied Physics Letters, 41 (4):346-347 [Details]
(1990)'Conduction mechanisms in thin-film accumulation-mode SOI p-channel MOSFETs'
Colinge, J (1990) 'Conduction mechanisms in thin-film accumulation-mode SOI p-channel MOSFETs'. Electron Devices, IEEE Transactions on, 37 (3):718-723 [Details]
(1996)'Design of SOI CMOS operational amplifiers for applications up to 300 C'
Eggermont, J-P and De Ceuster, Denis and Flandre, Denis and Gentinne, Bernard and Jespers, Paul GA and Colinge, J (1996) 'Design of SOI CMOS operational amplifiers for applications up to 300 C'. Solid-State Circuits, IEEE Journal of, 31 (2):179-186 [Details]
(1986)'Reduction of floating substrate effect in thin-film SOI MOSFETs'
Colinge, J-P (1986) 'Reduction of floating substrate effect in thin-film SOI MOSFETs'. Electronics Letters, 22 (4):187-188 [Details]
(2003)'Threshold voltage and subthreshold slope of multiple-gate SOI MOSFETs'
Colinge, JP and Park, JW and Xiong, W (2003) 'Threshold voltage and subthreshold slope of multiple-gate SOI MOSFETs'. Electron Device Letters, IEEE, 24 (8):515-517 [Details]
(2010)'Low subthreshold slope in junctionless multigate transistors'
Lee, Chi-Woo and Nazarov, Alexei N and Ferain, Isabelle and Akhavan, Nima Dehdashti and Yan, Ran and Razavi, Pedram and Yu, Ran and Doria, Rodrigo T and Colinge, Jean-Pierre (2010) 'Low subthreshold slope in junctionless multigate transistors'. Applied Physics Letters, 96 (10) [Details]
(1996)'A silicon-on-insulator quantum wire'
Colinge, JP and Baie, X and Bayot, Vincent and Grivei, E (1996) 'A silicon-on-insulator quantum wire'. Solid-State Electronics, 39 (1):49-51 [Details]
(1996)'Modelling and application of fully depleted SOI MOSFETs for low voltage, low power analogue CMOS circuits'
Flandre, Denis and Ferreira, LF and Jespers, PGA and Colinge, J-P (1996) 'Modelling and application of fully depleted SOI MOSFETs for low voltage, low power analogue CMOS circuits'. Solid-State Electronics, 39 (4):455-460 [Details]
(2007)'Device design guidelines for nano-scale MuGFETs'
Lee, Chi-Woo and Yun, Se-Re-Na and Yu, Chong-Gun and Park, Jong-Tae and Colinge, Jean-Pierre (2007) 'Device design guidelines for nano-scale MuGFETs'. Solid-state electronics, 51 (3):505-510 [Details]
(2006)'Quantum-mechanical effects in trigate SOI MOSFETs'
Colinge, J and Alderman, John C and Xiong, Weize and Cleavelin, C Rinn (2006) 'Quantum-mechanical effects in trigate SOI MOSFETs'. Electron Devices, IEEE Transactions on, 53 (5):1131-1136 [Details]
(1999)'High-frequency four noise parameters of silicon-on-insulator-based technology MOSFET for the design of low-noise RF integrated circuits'
Dambrine, Gilles and Raskin, J-P and Danneville, Fran\ccois and Vanhoenackel Janvier, D and Colinge, J and Cappy, Alain (1999) 'High-frequency four noise parameters of silicon-on-insulator-based technology MOSFET for the design of low-noise RF integrated circuits'. Electron Devices, IEEE Transactions on, 46 (8):1733-1741 [Details]
(1996)'Improvement of SOI MOS current-mirror performances using serial-parallel association of transistors'
De Ceuster, D and Flandre, Denis and Colinge, Jean-Pierre and Cristoloveanu, Sorin (1996) 'Improvement of SOI MOS current-mirror performances using serial-parallel association of transistors'. Electronics letters, 32 (4):278-279 [Details]
(2008)'Quantum-mechanical effects in nanometer scale MuGFETs'
Yun, Se Re Na and Yu, Chong Gun and Park, Jong Tae and Colinge, Jean Pierre (2008) 'Quantum-mechanical effects in nanometer scale MuGFETs'. Microelectronic Engineering, 85 (8):1717-1722 [Details]
(2012)'Emission and absorption of optical phonons in multigate silicon nanowire MOSFETs'
Akhavan, Nima Dehdashti and Ferain, Isabelle and Yu, Ran and Razavi, Pedram and Colinge, Jean-Pierre (2012) 'Emission and absorption of optical phonons in multigate silicon nanowire MOSFETs'. Journal of Computational Electronics, 11 (3):249-265 [Details]
(2002)'Two-dimensional self-consistent simulation of a triangular P-channel SOI nano-flash memory device'
Tang, Xiaohui and Baie, Xavier and Colinge, J and Gustin, Cedric and Bayot, Vincent (2002) 'Two-dimensional self-consistent simulation of a triangular P-channel SOI nano-flash memory device'. Electron Devices, IEEE Transactions on, 49 (8):1420-1426 [Details]
(1981)'A high density CMOS inverter with stacked transistors'
Colinge, JP and Demoulin, E and others (1981) 'A high density CMOS inverter with stacked transistors'. IEEE Electron Device Letters, (10):250-251 [Details]
(1983)'Localisation of defects on SOI films via selective recrystallisation using halogen lamps'
Bensahel, D and Haond, M and Vu, DP and Colinge, JP (1983) 'Localisation of defects on SOI films via selective recrystallisation using halogen lamps'. Electronics Letters, 19 (13):464-466 [Details]
(2012)'Subthreshold behavior of junctionless silicon nanowire transistors from atomic scale simulations'
Ansari, Lida and Feldman, Baruch and Fagas, Giorgos and Colinge, Jean-Pierre and Greer, James C (2012) 'Subthreshold behavior of junctionless silicon nanowire transistors from atomic scale simulations'. Solid-State Electronics, 71 :58-62 [Details]
(1996)'Improved LOCOS isolation for thin-film SOI MOSFETs'
Colinge, JP and Crahay, Andr\'e and De Ceuster, D and Dessard, V and Gentinne, B (1996) 'Improved LOCOS isolation for thin-film SOI MOSFETs'. Electronics Letters, 32 (19):1834-1835 [Details]
(2004)'Temperature dependence of DTMOS transistor characteristics'
Lee, Jae-Ki and Choi, Nag-Jong and Yu, Chong-Gun and Colinge, Jean-Pierre and Park, Jong-Tae (2004) 'Temperature dependence of DTMOS transistor characteristics'. Solid-State Electronics, 48 (1):183-187 [Details]
(1983)'Growth of large areas of grain boundary-free silicon-on-insulator'
Colinge, JP and Bensahel, D and Alamome, M and Haond, M and Pfister, JC (1983) 'Growth of large areas of grain boundary-free silicon-on-insulator'. Electronics Letters, 19 (23):985-986 [Details]
(2011)'Physics of gate modulated resonant tunneling (RT)-FETs: multi-barrier MOSFET for steep slope and high on-current'
Afzalian, Aryan and Colinge, Jean-Pierre and Flandre, Denis (2011) 'Physics of gate modulated resonant tunneling (RT)-FETs: multi-barrier MOSFET for steep slope and high on-current'. Solid-State Electronics, 59 (1):50-61 [Details]
(1993)'Analysis of drain breakdown voltage in enhancement-mode SOI MOSFETs'
Smeys, P and Colinge, JP (1993) 'Analysis of drain breakdown voltage in enhancement-mode SOI MOSFETs'. Solid-state electronics, 36 (4):569-573 [Details]
(1997)'Research of high-temperature instability processes in buried dielectric of full depleted SOI MOSFET's'
Nazarov, AN and Colinge, J-P and Barchuk, IP (1997) 'Research of high-temperature instability processes in buried dielectric of full depleted SOI MOSFET's'. Microelectronic engineering, 36 (1):363-366 [Details]
(2001)'Hall effect measurements in double-gate SOI MOSFETs'
Vandooren, Anne and Cristoloveanu, S and Flandre, D and Colinge, Jean-Pierre (2001) 'Hall effect measurements in double-gate SOI MOSFETs'. Solid-State Electronics, 45 (10):1793-1798 [Details]
(2012)'Influence of discrete dopant on quantum transport in silicon nanowire transistors'
Akhavan, Nima Dehdashti and Ferain, Isabelle and Yu, Ran and Razavi, Pedram and Colinge, Jean-Pierre (2012) 'Influence of discrete dopant on quantum transport in silicon nanowire transistors'. Solid-State Electronics, 70 :92-100 [Details]
(1993)'Circuit element with elimination of kink effect'
Colinge, Jean P and Gao, Ming H (1993) 'Circuit element with elimination of kink effect'. [Details]
(2011)'Quantum confinement effects in capacitance behavior of multigate silicon nanowire MOSFETs'
Afzalian, Aryan and Lee, Chi-Woo and Akhavan, Nima Dehdashti and Yan, Ran and Ferain, Isabelle and Colinge, J (2011) 'Quantum confinement effects in capacitance behavior of multigate silicon nanowire MOSFETs'. Nanotechnology, IEEE Transactions on, 10 (2):300-309 [Details]
(1998)'Fabrication of twin nano silicon wires based on arsenic dopant effect'
Tang, Xiaohui and Baie, Xavier and Colinge, Jean-Pierre (1998) 'Fabrication of twin nano silicon wires based on arsenic dopant effect'. Japanese journal of applied physics, 37 (3S) [Details]
(2011)'Influence of elastic and inelastic electron--phonon interaction on quantum transport in multigate silicon nanowire MOSFETs'
Akhavan, Nima Dehdashti and Afzalian, Aryan and Kranti, Abhinav and Ferain, Isabelle and Lee, Chi-Woo and Yan, Ran and Razavi, Pedram and Yu, Ran and Colinge, J (2011) 'Influence of elastic and inelastic electron--phonon interaction on quantum transport in multigate silicon nanowire MOSFETs'. Electron Devices, IEEE Transactions on, 58 (4):1029-1037 [Details]
(2012)'Influence of channel material properties on performance of nanowire transistors'
Razavi, Pedram and Fagas, Giorgos and Ferain, Isabelle and Yu, Ran and Das, Samaresh and Colinge, Jean-Pierre (2012) 'Influence of channel material properties on performance of nanowire transistors'. Journal of Applied Physics, 111 (12) [Details]
(1983)'Transistors made in single-crystal SOI films'
Colinge, JP and Demoulin, E and Bensahel, D and Auvert, G and Morel, H (1983) 'Transistors made in single-crystal SOI films'. Electron Device Letters, IEEE, 4 (4):75-77 [Details]
(2008)'Drain breakdown voltage in MuGFETs: influence of physical parameters'
Lee, Chi-Woo and Afzalian, Aryan and Yan, Ran and DEHDASHTI AKHAVAN, Nima and Xiong, Weize and Colinge, Jean-Pierre (2008) 'Drain breakdown voltage in MuGFETs: influence of physical parameters'. IEEE transactions on electron devices, 55 (12):3503-3506 [Details]
(1985)'Fabrication of thin silicon-on-insulator flims using laser recrystallisation'
Colinge, JP and Hu, HK and Peng, S (1985) 'Fabrication of thin silicon-on-insulator flims using laser recrystallisation'. Electronics letters, 21 (23):1102-1103 [Details]
(2000)'Accurate characterization of silicon-on-insulator mosfets for the design of low-voltage, Low-Power RF Integrated Circuits'
Raskin, J-P and Gilon, R and Dambrine, G and Chen, J and Vanhoenacker, D and Colinge, J-P (2000) 'Accurate characterization of silicon-on-insulator mosfets for the design of low-voltage, Low-Power RF Integrated Circuits'. Analog Integrated Circuits and Signal Processing, 25 (2):133-155 [Details]
(2012)'Negative-bias-temperature-instability and hot carrier effects in nanowire junctionless p-channel multigate transistors'
Park, Jong Tae and Kim, Jin Young and Colinge, Jean Pierre (2012) 'Negative-bias-temperature-instability and hot carrier effects in nanowire junctionless p-channel multigate transistors'. Applied Physics Letters, 100 (8) [Details]
(2011)'Analog Operation Temperature Dependence of nMOS Junctionless Transistors Focusing on Harmonic Distortion'
Doria, Rodrigo T and Pavanello, Marcelo A and Trevisoli, Renan D and de Souza, Michelly and Lee, Chi-Woo and Ferain, Isabelle and Akhavan, N and Yan, Ran and Razavi, Pedram and Yu, Ran and others (2011) 'Analog Operation Temperature Dependence of nMOS Junctionless Transistors Focusing on Harmonic Distortion'. Journal of Integrated Circuits and Systems, 6 (1):114-121 [Details]
(2004)'High-power SOI vertical DMOS transistors with lateral drain contacts: Process developments, characterization, and modeling'
Pinardi, Kuntjoro and Heinle, Ulrich and Bengtsson, Stefan and Olsson, J\"orgen and Colinge, J (2004) 'High-power SOI vertical DMOS transistors with lateral drain contacts: Process developments, characterization, and modeling'. Electron Devices, IEEE Transactions on, 51 (5):790-796 [Details]
(1986)'pin photodiodes made in laser-recrystallized silicon-on-insulator'
Colinge, J (1986) 'pin photodiodes made in laser-recrystallized silicon-on-insulator'. Electron Devices, IEEE Transactions on, 33 (2):203-205 [Details]
(1986)'A lateral COMFET made in thin silicon-on-insulator film'
Colinge, J and Chiang, Shang-Yi (1986) 'A lateral COMFET made in thin silicon-on-insulator film'. Electron Device Letters, IEEE, 7 (12):697-699 [Details]
(1997)'Total gamma dose characteristics of CMOS devices in SOI structures based on oxidized porous silicon'
Bondarenko, VP and Bogatirev, YV and Colinge, JP and Dolgyi, LN and Dorofeev, AM and Yakovtseva, VA (1997) 'Total gamma dose characteristics of CMOS devices in SOI structures based on oxidized porous silicon'. Nuclear Science, IEEE Transactions on, 44 (5):1719-1723 [Details]
(2004)'Electrothermal simulations of high-power SOI vertical DMOS transistors with lateral drain contacts under unclamped inductive switching test'
Pinardi, Kuntjoro and Heinle, Ulrich and Bengtsson, Stefan and Olsson, J\"orgen and Colinge, Jean-Pierre (2004) 'Electrothermal simulations of high-power SOI vertical DMOS transistors with lateral drain contacts under unclamped inductive switching test'. Solid-State Electronics, 48 (7):1119-1126 [Details]
(1995)'Theoretical considerations for SRAM total-dose hardening'
Francis, P and Flandre, Denis and Colinge, Jean-Pierre (1995) 'Theoretical considerations for SRAM total-dose hardening'. Nuclear Science, IEEE Transactions on, 42 (2):83-91 [Details]
(1983)'The use of selective annealing for growing very large grains in silicon on insulator films'
Colinge, JP and Demoulin, E and Bensahel, D and Auvert, G (1983) 'The use of selective annealing for growing very large grains in silicon on insulator films'. Japanese Journal of Applied Physics, 22 (S1) [Details]
(2011)'Energy-band engineering for improved charge retention in fully self-aligned double floating-gate single-electron memories'
Tang, Xiaohui and Krzeminski, Christophe and Lecavelier des Etangs-Levallois, Aure´lien and Chen, Zhenkun and Dubois, Emmanuel and Kasper, Erich and Karmous, Alim and Reckinger, Nicolas and Flandre, Denis and Francis, Laurent A and others (2011) 'Energy-band engineering for improved charge retention in fully self-aligned double floating-gate single-electron memories'. Nano letters, 11 (11):4520-4526 [Details]
(1997)'Comparison of self-heating effect in GAA and SOI mosfets'
Francis, P and Colinge, JP and Flandre, Denis (1997) 'Comparison of self-heating effect in GAA and SOI mosfets'. Microelectronics Reliability, 37 (1):61-75 [Details]
(1998)'SILICON-ON-INSULATOR TECHNOLOGY-Silicon-on-Insulator Technology'
Colinge, JP and Bower, RW (1998) 'SILICON-ON-INSULATOR TECHNOLOGY-Silicon-on-Insulator Technology'. MRS Bulletin-Materials Research Society, 23 (12):13-15 [Details]
(2009)'NBTI and hot-carrier effects in accumulation-mode Pi-gate pMOSFETs'
Lee, Chi-Woo and Ferain, Isabelle and Afzalian, Aryan and Yan, Ran and Dehdashti, Nima and Razavi, Pedram and Colinge, Jean-Pierre and Park, Jong Tae (2009) 'NBTI and hot-carrier effects in accumulation-mode Pi-gate pMOSFETs'. Microelectronics Reliability, 49 (9):1044-1047 [Details]
(2002)'Hot carrier-induced SOI MOSFET degradation under AC stress conditions'
Lee, Jae-Ki and Choi, Nag-Jong and Hyun, Yun-Bong and Yu, Chong-Gun and Colinge, J and Park, Jong-Tae (2002) 'Hot carrier-induced SOI MOSFET degradation under AC stress conditions'. Electron Device Letters, IEEE, 23 (3):157-159 [Details]
(1991)'An overview of CMOS-SOI technology and its potential use in particle detection systems'
Colinge, Jean-Pierre (1991) 'An overview of CMOS-SOI technology and its potential use in particle detection systems'. Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 305 (3):615-619 [Details]
(2002)'Unclamped inductive switching behaviour of high power SOI vertical DMOS transistors with lateral drain contacts'
Pinardi, Kuntjoro and Heinle, Ulrich and Bengtsson, Stefan and Olsson, J\"orgen and Colinge, Jean-Pierre (2002) 'Unclamped inductive switching behaviour of high power SOI vertical DMOS transistors with lateral drain contacts'. Solid-State Electronics, 46 (12):2105-2110 [Details]
(2011)'Nanowire to Single-Electron Transistor Transition in Trigate SOI MOSFETs'
Akhavan, Nima Dehdashti and Afzalian, Aryan and Lee, Chi-Woo and Yan, Ran and Ferain, Isabelle and Razavi, Pedram and Yu, Ran and Fagas, Giorgos and Colinge, J (2011) 'Nanowire to Single-Electron Transistor Transition in Trigate SOI MOSFETs'. Electron Devices, IEEE Transactions on, 58 (1):26-32 [Details]
(2002)'Temperature dependence of hot-carrier degradation in silicon-on-insulator dynamic threshold voltage MOS transistors'
Lee, Jae-Ki and Choi, Nag-Jong and Yu, Chong-Gun and Colinge, J and Park, Jong-Tae (2002) 'Temperature dependence of hot-carrier degradation in silicon-on-insulator dynamic threshold voltage MOS transistors'. Electron Device Letters, IEEE, 23 (11):673-675 [Details]
(1996)'Measurement and modeling of thin-film accumulation-mode SOI< i> p-MOSFET intrinsic gate capacitances'
Gentinne, B and Flandre, Denis and Colinge, J-P (1996) 'Measurement and modeling of thin-film accumulation-mode SOI< i> p-MOSFET intrinsic gate capacitances'. Solid-State Electronics, 39 (7):1071-1078 [Details]
(2009)'Comparison of different surface orientation in narrow fin MuGFETs'
Lee, Chi-Woo and Afzalian, Aryan and Ferain, Isabelle and Yan, Ran and Dehdashti, Nima and Byun, Ki-Yeol and Colinge, Cynthia and Xiong, Weize and Colinge, Jean-Pierre (2009) 'Comparison of different surface orientation in narrow fin MuGFETs'. Microelectronic Engineering, 86 (12):2381-2384 [Details]
(1999)'Carrier lifetime extraction in fully depleted dual-gate SOI devices'
Ernst, T and Vandooren, A and Cristoloveanu, S and Colinge, JP and Flandre, D (1999) 'Carrier lifetime extraction in fully depleted dual-gate SOI devices'. IEEE Electron Device Letters, 20 (5):209-211 [Details]
(1992)'Trends in silicon-on-insulator technology'
Colinge, Jean-Pierre (1992) 'Trends in silicon-on-insulator technology'. Microelectronic Engineering, 19 (1):795-802 [Details]
(1996)'Measurement and two-dimensional simulation of thin-film SOI MOSFETs: Intrinsic gate capacitances at elevated temperatures'
Gentinne, B and Flandre, Denis and Colinge, J-P and Van De Wiele, Fernand (1996) 'Measurement and two-dimensional simulation of thin-film SOI MOSFETs: Intrinsic gate capacitances at elevated temperatures'. Solid-State Electronics, 39 (11):1613-1619 [Details]
(2012)'Resist--substrate interface tailoring for generating high-density arrays of Ge and Bi2Se3 nanowires by electron beam lithography'
Hobbs, Richard G and Schmidt, Michael and Bolger, Ciara T and Georgiev, Yordan M and Fleming, Peter and Morris, Michael A and Petkov, Nikolay and Holmes, Justin D and Xiu, Faxian and Wang, Kang L and others (2012) 'Resist--substrate interface tailoring for generating high-density arrays of Ge and Bi2Se3 nanowires by electron beam lithography'. Journal of Vacuum Science \& Technology B, 30 (4) [Details]
(1997)'Study on titanium salicide process for thin-film SOI devices'
Chen, Jian and Colinge, Jean-Pierre (1997) 'Study on titanium salicide process for thin-film SOI devices'. Microelectronic engineering, 33 (1):189-194 [Details]
(2003)'Multiple-gate silicon-on-insulator MOS transistors'
Colinge, Jean-Pierre (2003) 'Multiple-gate silicon-on-insulator MOS transistors'. Proceedings-Electrochemical Society, :2-17 [Details]
(2009)'Analytical model for the high-temperature behaviour of the subthreshold slope in MuGFETs'
Lee, Chi-Woo and Lederer, Dimitri and Afzalian, Aryan and Yan, Ran and Akhavan, Nima Dehdashti and Colinge, Jean-Pierre (2009) 'Analytical model for the high-temperature behaviour of the subthreshold slope in MuGFETs'. Microelectronic engineering, 86 (10):2067-2071 [Details]
(1997)'Analytical modeling of the substrate influences on accumulation-mode SOI< i> p MOSFETs at room temperature and at liquid nitrogen temperature'
Pavanello, Marcelo Antonio and Martino, Jo\~ao Antonio and Colinge, Jean-Pierre (1997) 'Analytical modeling of the substrate influences on accumulation-mode SOI< i> p MOSFETs at room temperature and at liquid nitrogen temperature'. Solid-State Electronics, 41 (9):1241-1246 [Details]
(1987)'Voltage-controlled bipolar-MOS (VCBM) ring oscillator'
Colinge, JP (1987) 'Voltage-controlled bipolar-MOS (VCBM) ring oscillator'. Electronics Letters, 23 (19):1023-1025 [Details]
(1992)'Correlation between spectroscopic reflectrometry and electrical measurements of SIMOX SOI film thickness'
Smeys, P and Magnusson, U and Colinge, JP (1992) 'Correlation between spectroscopic reflectrometry and electrical measurements of SIMOX SOI film thickness'. Microelectronic Engineering, 19 (1):823-826 [Details]
(2001)'Influence of device geometry on SOI single-hole transistor characteristics'
Tang, Xiaohui and Baie, Xavier and Colinge, Jean-Pierre and Loumaye, Pierre and Renaux, Christian and Bayot, Vincent (2001) 'Influence of device geometry on SOI single-hole transistor characteristics'. Microelectronics Reliability, 41 (11):1841-1846 [Details]
(1999)'„Parameter extraction for buried oxide trap from high-temperature kinkeffect of back-channel SOI n-MOSFET”'
Nazarov, AN and Barchuk, IP and Lysenko, VS and Colinge, JP (1999) '„Parameter extraction for buried oxide trap from high-temperature kinkeffect of back-channel SOI n-MOSFET”'. Silicon-on-Insulator Technology and Devices 99, 3 :299-304 [Details]
(2010)'Analog Operation and Harmonic Distortion Temperature Dependence of nMOS Junctionless Transistors'
Doria, Rodrigo T and Pavanello, Marcelo A and Lee, Chi-Woo and Ferain, Isabelle and Dehdashti-Akhavan, Nima and Yan, Ran and Razavi, Pedram and Yu, Ran and Kranti, Abhinav and Colinge, Jean-Pierre (2010) 'Analog Operation and Harmonic Distortion Temperature Dependence of nMOS Junctionless Transistors'. ECS Transactions, 31 (1):13-20 [Details]
(1988)'SILICON-ON-INSULATOR MOS DEVICES FOR INTEGRATED-CIRCUIT APPLICATIONS'
Colinge, JP (1988) 'SILICON-ON-INSULATOR MOS DEVICES FOR INTEGRATED-CIRCUIT APPLICATIONS'. Hewlett-Packard Journal, 39 (1):87-93 [Details]
(1984)'CMOS circuits made in lamp-recrystallised silicon-on-insulator'
Vu, DP and Leguet, C and Haond, M and Bensahel, D and Colinge, JP (1984) 'CMOS circuits made in lamp-recrystallised silicon-on-insulator'. Electronics Letters, 20 (7):298-299 [Details]
(2003)'Increased hot carrier effects in Gate-All-Around SOI nMOSFET’s'
Tae Park, Jong and Jong Choi, Nag and Gun Yu, Chong and Hee Jeon, Seok and Colinge, Jean-Pierre (2003) 'Increased hot carrier effects in Gate-All-Around SOI nMOSFET’s'. Microelectronics Reliability, 43 (9-11):1427-1432 [Details]
(1992)'Low temperature behaviour of submicron accumulation mode p-channel SOI MOSFETs'
Rotondaro, ALP and Magnusson, U and Simoen, E and Claeys, Cor and Colinge, JP (1992) 'Low temperature behaviour of submicron accumulation mode p-channel SOI MOSFETs'. Microelectronic Engineering, 19 (1):857-860 [Details]
(2008)'Influence of carrier confinement on the subthreshold swing of multigate silicon-on-insulator transistors'
Colinge, Jean-Pierre and Afzalian, Aryan and Lee, Chi-Woo and Yan, Ran and Akhavan, Nima Dehdashti (2008) 'Influence of carrier confinement on the subthreshold swing of multigate silicon-on-insulator transistors'. Applied Physics Letters, 92 (13) [Details]
(1995)'Tungsten metallization technology for high temperature silicon-on-insulator devices'
Chen, Jian and Colinge, J-P (1995) 'Tungsten metallization technology for high temperature silicon-on-insulator devices'. Materials Science and Engineering: B, 29 (1):18-20 [Details]
(2011)'Field-effect mobility extraction in nanowire field-effect transistors by combination of transfer characteristics and random telegraph noise measurements'
Nazarov, AN and Ferain, I and Akhavan, N Dehdashti and Razavi, P and Yu, R and Colinge, JP (2011) 'Field-effect mobility extraction in nanowire field-effect transistors by combination of transfer characteristics and random telegraph noise measurements'. Applied Physics Letters, 99 (7) [Details]
(2011)'A Simulation comparison between junctionless and inversion-mode MuGFETs'
Colinge, Jean-Pierre and Kranti, Abhinav and Yan, Ran and Ferain, Isabelle and Akhavan, Nima Dehdashti and Razavi, Pedram and Lee, Chi-Woo and Yu, Ran and Colinge, Cindy (2011) 'A Simulation comparison between junctionless and inversion-mode MuGFETs'. ECS Transactions, 35 (5):63-72 [Details]
(1997)'Potential and modelling of 1 $\mu$m 1 GHz SOI CMOS OTAs'
Eggermont, Jean-Pierre and Flandre, Denis and Raskin, Jean-Pierre and Colinge, Jean-Pierre (1997) 'Potential and modelling of 1 $\mu$m 1 GHz SOI CMOS OTAs'. Electronics Letters, 33 (9):774-775 [Details]
(2010)'LDD and back-gate engineering for fully depleted planar SOI transistors with thin buried oxide'
Yan, Ran and Duane, Russell and Razavi, Pedram and Afzalian, Aryan and Ferain, Isabelle and Lee, Chi-Woo and Akhavan, Nima Dehdashti and Nguyen, Bich-Yen and Bourdelle, Konstantin K and Colinge, J (2010) 'LDD and back-gate engineering for fully depleted planar SOI transistors with thin buried oxide'. Electron Devices, IEEE Transactions on, 57 (6):1319-1326 [Details]
(2008)'Ultra scaled multigate SOI MOSFETs: Accumulation-mode vs. inversion-mode'
Afzalian, Aryan and Lederer, Dimitri and Lee, Chi-Woo and Yan, Ran and Colinge, Jean-Pierre and others (2008) 'Ultra scaled multigate SOI MOSFETs: Accumulation-mode vs. inversion-mode'. Proceed-ings of 4th EuroSOI Workshop, :47-48 [Details]
(1999)'Association of high-temperature kink-effect in SIMOX SOI fully depleted n-MOSFET with bias temperature instability of buried oxide'
Nazarov, AN and Barchuk, IP and Lysenko, VS and Colinge, J-P (1999) 'Association of high-temperature kink-effect in SIMOX SOI fully depleted n-MOSFET with bias temperature instability of buried oxide'. Microelectronic engineering, 48 (1):379-382 [Details]
(1991)'Short channel effect in thin-film accumulation-mode p-channel SOI MOSFETs'
Smeys, P and Clerix, A and Colinge, J-P (1991) 'Short channel effect in thin-film accumulation-mode p-channel SOI MOSFETs'. Electronics Letters, 27 (11):970-971 [Details]
(2012)'Junctionless metal-oxide-semiconductor transistor'
Colinge, Jean-Pierre (2012) 'Junctionless metal-oxide-semiconductor transistor'. [Details]
(1997)'Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77 K'
Pavanello, Marcelo Antonio and Martino, Jo\~ao Antonio and Colinge, Jean-Pierre (1997) 'Analytical modeling of the substrate effect on accumulation-mode SOI pMOSFETs at room temperature and at 77 K'. Microelectronic engineering, 36 (1):375-378 [Details]
(1983)'Beam-Recrystallized Device-Worthy Films of Si on SiO2 via Control of the Grain Boundary Location'
Colinge, JP and Bensahel, D and Alamome, M and Haond, M and Leguet, C (1983) 'Beam-Recrystallized Device-Worthy Films of Si on SiO2 via Control of the Grain Boundary Location'. MRS Proceedings, 23 [Details]
(2009)'Three-Dimensional NEGF Simulations of Constriction Tunnel Barrier Silicon Nanowire MUGFETs'
Afzalian, Aryan and Lee, Chi-Woo and Yan, Ran and Akhavan, Nima Dehdashti and Colinge, Cindy and Colinge, Jean-Pierre (2009) 'Three-Dimensional NEGF Simulations of Constriction Tunnel Barrier Silicon Nanowire MUGFETs'. ECS Transactions, 19 (4):229-234 [Details]
(2010)'Influence of gate misalignment on the electrical characteristics of MuGFETS'
Lee, Chi-Woo and Afzalian, Aryan and Ferain, Isabelle and Yan, Ran and Akhavan, Nima Dehdashti and Xiong, Weize and Colinge, Jean-Pierre (2010) 'Influence of gate misalignment on the electrical characteristics of MuGFETS'. Solid-State Electronics, 54 (3):226-230 [Details]
(1995)'The ESD protection mechanisms and the related failure modes and mechanisms observed in SOI snapback nMOSFET's'
Verhaege, Koen and Groeseneken, Guido and Colinge, Jean-Pierre and Maes, Herman E (1995) 'The ESD protection mechanisms and the related failure modes and mechanisms observed in SOI snapback nMOSFET's'. Microelectronics Reliability, 35 (3):555-566 [Details]
(1992)'Physics and performances of accumulation-mode SOI p-MOSFET's from low (77 K) to high (150--320° C) temperatures'
Flandre, Denis and Terao, Akira and Loo, Thierry and Colinge, J-P (1992) 'Physics and performances of accumulation-mode SOI p-MOSFET's from low (77 K) to high (150--320° C) temperatures'. Microelectronic Engineering, 19 (1):803-806 [Details]
(2009)'Quantization effect in capacitance behavior of nanoscale Si MuGFETs'
Afzalian, Aryan and Lee, Chi-Woo and Yan, Ran and Dehdashti, Nima and Ferain, Isabelle and Colinge, Jean-Pierre and others (2009) 'Quantization effect in capacitance behavior of nanoscale Si MuGFETs'. Proceeding 5th EuroSOI Workshop, pp., Gotenborg, [Details]
(1998)'High-temperature characteristics of zone-melting recrystallized silicon-on-insulator MOSFETs'
Lysenko, VS and Rudenko, TE and Nazarov, AN and Kilchitskaya, VI and Rudenko, AN and Limanov, AB and Colinge, JP (1998) 'High-temperature characteristics of zone-melting recrystallized silicon-on-insulator MOSFETs'. Semiconductor Physics, Quantum Electronics and Optoelectronics, 1 (1):101-107 [Details]
(1994)'P+-P-P+ pseudo-bipolar lateral SOI transistor'
Colinge, Jean-Pierre and Flandre, Denis and De Ceuster, D (1994) 'P+-P-P+ pseudo-bipolar lateral SOI transistor'. Electronics Letters, 30 (18):1543-1545 [Details]
(1988)'Transconductance enhancement mechanisms in ultra-thin (\&les; 1000 \AA) silicon-on-insulator MOSFETs'
Sturm, JC and Tokunaga, K and Colinge, J-P (1988) 'Transconductance enhancement mechanisms in ultra-thin (\&les; 1000 \AA) silicon-on-insulator MOSFETs'. Electron Devices, IEEE Transactions on, 35 (12):2431-2432 [Details]
(2004)'LETTERS-Silicon Devices-Body Effect in Tri-and Pi-Gate SOI MOSFETs'
Frei, J and Johns, C and Vazquez, A and Xiong, W and Cleavelin, CR and Schulz, T and Chaudhary, N and Gebara, G and Zaman, JR and Gostkowski, M and others (2004) 'LETTERS-Silicon Devices-Body Effect in Tri-and Pi-Gate SOI MOSFETs'. IEEE Electron Device Letters, 25 (12):813-815 [Details]
(2003)'Nature of high-temperature charge instability in fully depleted SOI MOSFETs'
Nazarov, AN and Lysenko, VS and COLINGE, J-P and Flandre, Denis (2003) 'Nature of high-temperature charge instability in fully depleted SOI MOSFETs'. Proceedings-Electrochemical Society, :455-460 [Details]
(2011)'The Roles of the Electric Field and the Density of Carriers in the Improved Output Conductance of Junctionless Nanowire Transistors'
Doria, Rodrigo T and Pavanello, Marcelo A and Trevisoli, Renan D and De Souza, Michelly and Lee, Chi-Woo and Ferain, Isabelle and Akhavan, Nima Dehdashti and Yan, Ran and Razavi, Pedram and Yu, Ran and others (2011) 'The Roles of the Electric Field and the Density of Carriers in the Improved Output Conductance of Junctionless Nanowire Transistors'. ECS Transactions, 35 (5):283-288 [Details]
(2004)'Reduced hot carrier effects in self-aligned ground-plane FDSOI MOSFET's'
YUN, SE RE NA and YU, CHONG GUN and JEON, SEOK HEE and KIM, CHUNG KYUE and PARK, JONG TAE and COLINGE, Jean Pierre (2004) 'Reduced hot carrier effects in self-aligned ground-plane FDSOI MOSFET's'. Microelectronics and reliability, 44 (9-11):1649-1654 [Details]
(1983)'Beam-recrystallised silicon-on-insulator films: can devices lives with grain boundaries?'
Colinge, Jean-Pierre (1983) 'Beam-recrystallised silicon-on-insulator films: can devices lives with grain boundaries?'. Microelectronics Journal, 14 (6):58-65 [Details]
(1993)'Non-destructive characterisation of SOI wafers using spectroscopic reflectrometry'
Smeys, P and Magnusson, U and Colinge, JP (1993) 'Non-destructive characterisation of SOI wafers using spectroscopic reflectrometry'. Solid-state electronics, 36 (8):1213-1216 [Details]
(1999)'DRAINCONDUCTANCEDEGRADATIONINGATE-ALL-AROUND INVERSION-MODE nMOSFETs WITH TOTAL DOSE'
Vandooren, A and Colinge, JP (1999) 'DRAINCONDUCTANCEDEGRADATIONINGATE-ALL-AROUND INVERSION-MODE nMOSFETs WITH TOTAL DOSE'. Silicon-on-insulator Technology and Devices: Proceedings of the Ninth International Symposium on Silicon-on-Insulator Technology and Devices, 99 (3) [Details]
(2009)'Quantization effect in capacitance behavior of nanoscale silicon multigate MOSFETs'
Afzalian, Aryan and Lee, Chi-Woo and Yan, Ran and Akhavan, Nima Dehdashti and Colinge, Cindy and Colinge, Jean-Pierre (2009) 'Quantization effect in capacitance behavior of nanoscale silicon multigate MOSFETs'. ECS Transactions, 19 (4):321-327 [Details]
(2013)'Impact ionization induced dynamic floating body effect in junctionless transistors'
Yu, R and Nazarov, AN and Lysenko, VS and Das, S and Ferain, I and Razavi, P and Shayesteh, M and Kranti, A and Duffy, R and Colinge, J-P (2013) 'Impact ionization induced dynamic floating body effect in junctionless transistors'. Solid-State Electronics, 90 :28-33 [Details]
(2001)'Future SOI Technology and Devices'
Colinge, J-P and Park, J-T (2001) 'Future SOI Technology and Devices'. SOLID STATE DEVICES AND MATERIALS, :238-239 [Details]
(2009)'Junctionless MuGFETs'
Lee, Chi-Woo and Afzalian, Aryan and Yan, Ran and Dehdashti, Nima and Colinge, Jean-Pierre and others (2009) 'Junctionless MuGFETs'. Proceedings EUROSOI Conference, :21-22 [Details]
(2008)'Doping Fluctuation Effects in Trigate SOI MOSFETs'
Yan, Ran and Lynch, Danny and Cayron, Thibault and Lederer, Dimitri and Afzalian, Aryan and Lee, Chi-Woo and Colinge, Jean-Pierre and others (2008) 'Doping Fluctuation Effects in Trigate SOI MOSFETs'. Proceeding 4th EuroSOI workshop, :63-64 [Details]
(2007)'3D simulation of doping fluctuation effects in trigate FETs'
Yan, Ran and Lynch, Danny and Cayron, Thibault and Lederer, Dimitri and Afzalian, Aryan and Lee, Chi-Woo and Colinge, JP (2007) '3D simulation of doping fluctuation effects in trigate FETs'. Proceedings of the COMSOL Users Conference, Grenoble, France, [Details]
(2012)'Method for Increasing Fin Density'
Colinge, Jean-Pierre (2012) 'Method for Increasing Fin Density'. [Details]
(1992)'VISIBLE LIGHT CHARACTERISATION OF SILICON ON INSULATOR MATERIALS'
Vanhellemont, J and Roussel, P and De Wolf, I and Smeys, P and Colinge, JP and Maes, HE (1992) 'VISIBLE LIGHT CHARACTERISATION OF SILICON ON INSULATOR MATERIALS'. Key Engineering Materials, 65 :133-140 [Details]
(2011)'Comparative Study of Random Telegraph Noise in Junctionless and Inversion-Mode MuGFETs'
Nazarov, Aleksey and Lee, Chi-Woo and Kranti, Abhinav and Ferain, Isabelle and Yan, Ran and Akhavan, Nima Dehdashti and Razavi, Pedram and Yu, Ran and Colinge, Jean-Pierre (2011) 'Comparative Study of Random Telegraph Noise in Junctionless and Inversion-Mode MuGFETs'. ECS Transactions, 35 (5):73-78 [Details]
(1998)'Silicon-on-Insulator for RF and microwave low-power applications'
Gillon, Renaud and Colinge, Jean-Pierre and Flandre, Denis and Raskin, Jean-Pierre and Vanhoenacker-Janvier, Danielle and others (1998) 'Silicon-on-Insulator for RF and microwave low-power applications'. Microwave engineering Europe, [Details]
(2013)'Method for fabricating a finfet device including a stem region of a fin element'
Colinge, Jean-Pierre and Ching, Kuo-Cheng and Wu, Zhiqiang (2013) 'Method for fabricating a finfet device including a stem region of a fin element'. [Details]
(1999)'SPECIAL SECTION ON 1998 EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE-SPECIAL SECTION PAPERS-Recombination Current Modeling and Carrier Lifetime Extraction in Dual-Gate Fully-Depleted SOI'
Ernst, T and Cristoloveanu, S and Vandooren, A and Rudenko, T and Colinge, JP (1999) 'SPECIAL SECTION ON 1998 EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE-SPECIAL SECTION PAPERS-Recombination Current Modeling and Carrier Lifetime Extraction in Dual-Gate Fully-Depleted SOI'. IEEE Transactions on Electron Devices, 46 (7):1503-1509 [Details]
(1994)'The ESD Protection Mechanisms and Related Failure Modes and Mechanisms Observed in SOI nMOSFET's'
Verhaege, K and Groeseneken, Guido and Colinge, Jean-Pierre and Maes, Herman (1994) 'The ESD Protection Mechanisms and Related Failure Modes and Mechanisms Observed in SOI nMOSFET's'. Microelectronics Reliability, 35 :555-556 [Details]
(2012)'Finfet having uniform doping profile and method of forming the same'
Colinge, Jean-Pierre and Hsieh, Wen-Hsing (2012) 'Finfet having uniform doping profile and method of forming the same'. [Details]
(1982)'MODELISATION DE TRANSISTORS MOS R\'EALIS\'ES DANS DU SILICIUM POLYCRISTALLIN A GROS GRAINS'
Morel, H and Colinge, J and Chante, J and others (1982) 'MODELISATION DE TRANSISTORS MOS R\'EALIS\'ES DANS DU SILICIUM POLYCRISTALLIN A GROS GRAINS'. Journal de Physique Colloques, 43 (C1) [Details]
(2007)'Short channel semiconductor device fabrication'
Colinge, Jean-Pierre and Xiong, Weize (2007) 'Short channel semiconductor device fabrication'. [Details]
(2000)'RECOMBINATION CURRENT IN FULLY-DEPLETED SOI DIODES: COMPACT MODEL AND LIFETIME EXTRACTION'
RUDENKO, TE and COLINGE, JP (2000) 'RECOMBINATION CURRENT IN FULLY-DEPLETED SOI DIODES: COMPACT MODEL AND LIFETIME EXTRACTION'. Perspectives, Science, and Technologies for Novel Silicon on Insulator Devices, Kyiv, Ukraine, 12-15 October 1998, 73 [Details]
(2010)'Simulations of gated Si nanowires and 3-nm junctionless transistors'
Ansari, Lida and Feldman, Baruch and Fagas, Giorgos and Colinge, Jean-Pierre and Greer, James C (2010) 'Simulations of gated Si nanowires and 3-nm junctionless transistors'. arXiv preprint arXiv:1003.4631, [Details]
(2015)'Fin Structure of Semiconductor Device'
Ching, Kuo-cheng and Wang, Chih-hao and Wu, Zhiqiang and Diaz, Carlos H and Colinge, Jean-pierre (2015) 'Fin Structure of Semiconductor Device'. [Details]
(2002)'Energy Band Theory'
Colinge, JP and Colinge, CA (2002) 'Energy Band Theory'. Physics of Semiconductor Devices, :1-49 [Details]
(2002)'The MOS Transistor'
Colinge, JP and Colinge, CA (2002) 'The MOS Transistor'. Physics of Semiconductor Devices, :165-250 [Details]
(1993)'Gate-All-Around Devices and Circuits'
Colinge, JP and Francis, P and Eggermond, JP and Flandre, D and Baie, X (1993) 'Gate-All-Around Devices and Circuits'. [Details]
(1986)'IIB-4 a high-speed, low-power buried-oxide SOI CMOS technology'
Colinge, JP and Kamins, TI and Chiang, SY and Liu, D and Peng, S and Rissman, P and Hashimoto, K (1986) 'IIB-4 a high-speed, low-power buried-oxide SOI CMOS technology'. Electron Devices, IEEE Transactions on, 33 (11):1842-1842 [Details]
(2002)'Metal-semiconductor Contacts'
Colinge, JP and Colinge, CA (2002) 'Metal-semiconductor Contacts'. Physics of Semiconductor Devices, :139-151 [Details]
(2009)'What is the killing advantage of multiple-gate SOI MOSFETs: electrostatics and scalability, transport or functionality?'
Christologique, S and Colinge, J-P and Fossum, J and Claeys, C and Balestra, F and Faynot, O and Monfray, S and others (2009) 'What is the killing advantage of multiple-gate SOI MOSFETs: electrostatics and scalability, transport or functionality?'. 5th EUROSOI Workshop, [Details]
(1987)'Erratum: CMOS circuits made in thin SIMOX films'
Colinge, JP and Kamins, TI (1987) 'Erratum: CMOS circuits made in thin SIMOX films'. Electronics Letters, 23 (25) [Details]
(1995)'Microelectronics education in Belgium'
Colinge, Jean-Pierre (1995) 'Microelectronics education in Belgium'. Materials Science and Engineering: A, 199 (1):39-43 [Details]
(2012)'Transistors with Wrapped-Around Gates and Methods for Forming the Same'
Colinge, Jean-Pierre and Ching, Kuo-Cheng (2012) 'Transistors with Wrapped-Around Gates and Methods for Forming the Same'. [Details]
(1999)'PAPERS-Solid-State Device Phenomena-High-Frequency Four Noise Parameters' of Silicon-on-Insulator-Based Technology MOSFET for the Design of Low-Noise RF Integrated Circuits'
Dambrine, G and Raskin, JP and Danneville, F and Vanhoenacker-Janvier, D and Colinge, JP and Cappy, A (1999) 'PAPERS-Solid-State Device Phenomena-High-Frequency Four Noise Parameters' of Silicon-on-Insulator-Based Technology MOSFET for the Design of Low-Noise RF Integrated Circuits'. IEEE Transactions on Electron Devices, 46 (8):1733-1741 [Details]
(1996)'Research into the Behavior of SOI Devices Operating in Extreme Environments'
Colinge, JP and Chen, J and Francis, P and Vandooren, A and Eggermont, JP (1996) 'Research into the Behavior of SOI Devices Operating in Extreme Environments'. [Details]
(2015)'FIN-TYPE FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING THE SAME'
Ching, Kuo-cheng and Wang, Chih-hao and Wu, Zhiqiang and Diaz, Carlos H and Colinge, Jean-pierre (2015) 'FIN-TYPE FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING THE SAME'. [Details]
(2014)'Self-Aligned Wrapped-Around Structure'
Colinge, Jean-pierre and Ching, Kuo-cheng and Guo, Ta-pen and Diaz, Carlos H (2014) 'Self-Aligned Wrapped-Around Structure'. [Details]
(2002)'The PN Junction Diode'
Colinge, JP and Colinge, CA (2002) 'The PN Junction Diode'. Physics of Semiconductor Devices, :95-137 [Details]
(1992)'Back-gate bias generator'
Smeys, P and Colinge, JP (1992) 'Back-gate bias generator'. Final Technical Report, 5 Jul. 1991-4 Jul. 1992 Interuniversity Micro-Electronics Center, Leuven (Belgium), 1 [Details]
(2002)'Generation/Recombination Phenomena'
Colinge, JP and Colinge, CA (2002) 'Generation/Recombination Phenomena'. Physics of Semiconductor Devices, :73-93 [Details]
(2014)'Method of fabricating a gate all around device'
Colinge, Jean-Pierre and Ching, Kuo-Cheng and Wu, Zhiqiang (2014) 'Method of fabricating a gate all around device'. [Details]
(2001)'High-temperature instability processes in SOI structures and MOSFETs'
Nazarov, AN and Kilchytska, VI and Vovk, Ja N and Colinge, JP (2001) 'High-temperature instability processes in SOI structures and MOSFETs'. Journal of Telecommunications and Information Technology, :18-26 [Details]
(2012)'Apparatus and Method for Forming Semiconductor Contacts'
Colinge, Jean-Pierre (2012) 'Apparatus and Method for Forming Semiconductor Contacts'. [Details]
(1982)'SIMULATION OF MOS-TRANSISTORS FABRICATED IN LARGE GRAIN POLYCRYSTALLINE SILICON'
MOREL, H and COLINGE, JP and CHANTE, JP (1982) 'SIMULATION OF MOS-TRANSISTORS FABRICATED IN LARGE GRAIN POLYCRYSTALLINE SILICON'. JOURNAL DE PHYSIQUE, 43 (NC 1):381-385 [Details]
(2012)'Comparison Between the Performance of Silicon Nanowire, Germanium Nanowire and Carbon Nanotube Junctionless Transistors from First Principle Calculations'
Ansari, Lida and Feldman, Baruch and Fagas, Giorgos and Colinge, Jean-Pierre and Greer, James (2012) 'Comparison Between the Performance of Silicon Nanowire, Germanium Nanowire and Carbon Nanotube Junctionless Transistors from First Principle Calculations'. Meeting Abstracts, (31):1184-1184 [Details]
(2013)'Method for Inducing Strain in Vertical Semiconductor Columns'
Colinge, Jean-Pierre and Chang, Gwan Sin and Diaz, Carlos H (2013) 'Method for Inducing Strain in Vertical Semiconductor Columns'. [Details]
(1997)'Silicon-on Insulator technology and applications'
Colinge, J-P (1997) 'Silicon-on Insulator technology and applications'. REVUE HF, :5-16 [Details]
(2011)'Transistor device'
Colinge, Jean-Pierre (2011) 'Transistor device'. [Details]
(1992)'Gate-All-Around Device'
Smeys, P and Colinge, JP (1992) 'Gate-All-Around Device'. [Details]
(1996)'La technologie du Silicium sur Isolant pour la microelectronique'
Haond, M and Colinge, J-P (1996) 'La technologie du Silicium sur Isolant pour la microelectronique'. BULLETIN SCIENTIFIQUE-ASSOCIATION DES INGENIEURS SORTIS DE L INSTITUT D ELECTRICITE MONTEFIORE, 109 :18-31 [Details]
(2012)'Aligned gate-all-around structure'
Ching, Kuo-Cheng and Colinge, Jean-Pierre and Wu, Zhiqiang (2012) 'Aligned gate-all-around structure'. [Details]
(2014)'Apparatus and Method for Forming Semiconductor Contacts'
Colinge, Jean-pierre (2014) 'Apparatus and Method for Forming Semiconductor Contacts'. [Details]
(2004)'Solid-State Power and High Voltage-High-Power SOI Vertical DMOS Transistors With Lateral Drain Contacts: Process Developments, Characterization, and Modeling'
Pinardi, K and Heinle, U and Bengtsson, S and Olsson, J and Colinge, JP (2004) 'Solid-State Power and High Voltage-High-Power SOI Vertical DMOS Transistors With Lateral Drain Contacts: Process Developments, Characterization, and Modeling'. IEEE Transactions on Electron Devices, 51 (5):790-796 [Details]
(2002)'Heterojunction Devices'
Colinge, JP and Colinge, CA (2002) 'Heterojunction Devices'. Physics of Semiconductor Devices, :315-330 [Details]
(2005)'2.33. SILICON-ON-INSULATOR GATE-ALL-AROUND DEVICE'
Colinge, JP and Gao, MH and Romano-Rodriguez, A and Maes, H and Claeys, C (2005) '2.33. SILICON-ON-INSULATOR GATE-ALL-AROUND DEVICE'. Emerging nanoelectronics: life with and after CMOS, 1 [Details]
(2014)'Tuning Strain in Semiconductor Devices'
Colinge, Jean-pierre and Ching, Kuo-cheng and Chang, Gwan Sin and Wu, Zhiqiang and Wang, Chih-hao and Diaz, Carlos H (2014) 'Tuning Strain in Semiconductor Devices'. [Details]
(2005)'2.35. MULTIPLE-GATE SOI MOSFETs: DEVICE DESIGN GUIDELINES'
Park, Jong-Tae and Colinge, Jean-Pierre (2005) '2.35. MULTIPLE-GATE SOI MOSFETs: DEVICE DESIGN GUIDELINES'. Emerging nanoelectronics: life with and after CMOS, 1 [Details]
(2002)'The Bipolar Transistor'
Colinge, JP and Colinge, CA (2002) 'The Bipolar Transistor'. Physics of Semiconductor Devices, :251-313 [Details]
(2002)'Semiconductor Processing'
Colinge, JP and Colinge, CA (2002) 'Semiconductor Processing'. Physics of Semiconductor Devices, :363-408 [Details]
(2013)'Finfet with dual workfunction gate structure'
Colinge, Jean-Pierre and Hsieh, Wen-Hsing (2013) 'Finfet with dual workfunction gate structure'. [Details]
(2014)'Method for inducing strain in FinFET channels'
Colinge, Jean-Pierre and Ching, Kuo-Cheng (2014) 'Method for inducing strain in FinFET channels'. [Details]
(2002)'Quantum-effect Devices'
Colinge, JP and Colinge, CA (2002) 'Quantum-effect Devices'. Physics of Semiconductor Devices, :331-362 [Details]
(1999)'High frequency four noise parameters of silicon--on insulator--based technology MOSFET: prospects for application to low noise RF integrated circuits'
Dambrine, Gilles and Raskin, Jean-Pierre and Picheta, L and Vanhoenacker, D and Colinge, Jean-Pierre and Cappy, A (1999) 'High frequency four noise parameters of silicon--on insulator--based technology MOSFET: prospects for application to low noise RF integrated circuits'. Electron Technology, 32 (1/2):81-87 [Details]
(2002)'Theory of Electrical Conduction'
Colinge, JP and Colinge, CA (2002) 'Theory of Electrical Conduction'. Physics of Semiconductor Devices, :51-72 [Details]
(2002)'Jfet and Mesfet'
Colinge, JP and Colinge, CA (2002) 'Jfet and Mesfet'. Physics of Semiconductor Devices, :153-164 [Details]
(2002)'Quasi-surrounding gate and a method of fabricating a silicon-on-insulator semiconductor device with the same'
Colinge, Jean Pierre and Diaz, Carlos H (2002) 'Quasi-surrounding gate and a method of fabricating a silicon-on-insulator semiconductor device with the same'. [Details]
(2011)'Junctionless nanowire transistor (JNT): properties and design guidelines'
Colinge, JP and Kranti, A and Yan, R and Lee, CW and Ferain, I and Yu, R and Dehdashti Akhavan, N and Razavi, P (2011) 'Junctionless nanowire transistor (JNT): properties and design guidelines'. Solid-State Electronics, 65 :33-37 [Details]
(2011)'Junctionless multiple-gate transistors for analog applications'
Doria, Rodrigo Trevisoli and Pavanello, Marcelo Antonio and Trevisoli, Renan Doria and de Souza, Michelly and Lee, Chi-Woo and Ferain, Isabelle and Akhavan, Nima Dehdashti and Yan, Ran and Razavi, Pedram and Yu, Ran and others (2011) 'Junctionless multiple-gate transistors for analog applications'. Electron Devices, IEEE Transactions on, 58 (8):2511-2519 [Details]
(1987)'Hot-electron effects in silicon-on-insulator n-channel MOSFET's'
Colinge, J (1987) 'Hot-electron effects in silicon-on-insulator n-channel MOSFET's'. Electron Devices, IEEE Transactions on, 34 (10):2173-2177 [Details]
(2010)'Simulation of junctionless Si nanowire transistors with 3 nm gate length'
Ansari, Lida and Feldman, Baruch and Fagas, Giorgos and Colinge, Jean-Pierre and Greer, James C (2010) 'Simulation of junctionless Si nanowire transistors with 3 nm gate length'. Applied Physics Letters, 97 (6) [Details]
(1990)'Performance and physical mechanisms in SIMOX MOS transistors operated at very low temperature'
Elewa, Tarek and Balestra, Francis and Cristoloveanu, SORIN and Hafez, ISMAIL M and Colinge, J and Auberton-Herve, A-J and Davis, JR (1990) 'Performance and physical mechanisms in SIMOX MOS transistors operated at very low temperature'. Electron Devices, IEEE Transactions on, 37 (4):1007-1019 [Details]
(2002)'Method of fabricating a silicon-on-insulator semiconductor device with an implanted ground plane'
Colinge, Jean Pierre and Diaz, Carlos H (2002) 'Method of fabricating a silicon-on-insulator semiconductor device with an implanted ground plane'. [Details]
(1993)'Demonstration of the potential of accumulation-mode MOS transistors on SOI substrattes for high-temperature operation (150-300° C)'
Flandre, Denis and Terao, A and Francis, P and Gentinne, B and Colinge, J-P (1993) 'Demonstration of the potential of accumulation-mode MOS transistors on SOI substrattes for high-temperature operation (150-300° C)'. IEEE electron device letters, 14 (1):10-12 [Details]
(1999)'Fully-depleted SOI CMOS technology for low-voltage low-power mixed digital/analog/microwave circuits'
Flandre, Denis and Colinge, JP and Chen, J and De Ceuster, D and Eggermont, JP and Ferreira, L and Gentinne, B and Jespers, PGA and Viviani, A and Gillon, R and others (1999) 'Fully-depleted SOI CMOS technology for low-voltage low-power mixed digital/analog/microwave circuits'. Analog Integrated Circuits and Signal Processing, 21 (3):213-228 [Details]
(1992)'Twin-MOSFET structure for suppression of kink and parasitic bipolar effects in SOI MOSFETs at room and liquid helium temperatures'
Gao, Minghui and Colinge, Jean-Pierre and Lauwers, Lode and Wu, Suhua and Clayes, Cor (1992) 'Twin-MOSFET structure for suppression of kink and parasitic bipolar effects in SOI MOSFETs at room and liquid helium temperatures'. Solid-state electronics, 35 (4):505-512 [Details]
(1981)'Grain size and resistivity of LPCVD polycrystalline silicon films'
Colinge, JP and Demoulin, E and Delannay, Francis and Lobet, M and Temerson, JM (1981) 'Grain size and resistivity of LPCVD polycrystalline silicon films'. Journal of The Electrochemical Society, 128 (9):2009-2014 [Details]
(1994)'Subthreshold slope of long-channel, accumulation-mode< i> p-channel SOI MOSFETs'
Colinge, Jean-Pierre and Flandre, Denis and Van de Wiele, Fernand (1994) 'Subthreshold slope of long-channel, accumulation-mode< i> p-channel SOI MOSFETs'. Solid-state electronics, 37 (2):289-294 [Details]
(1988)'Thin-film SOI devices: A perspective'
Colinge, Jean-Pierre (1988) 'Thin-film SOI devices: A perspective'. Microelectronic Engineering, 8 (3):127-147 [Details]
(2007)'Quantum-wire effects in trigate SOI MOSFETs'
Colinge, Jean-Pierre (2007) 'Quantum-wire effects in trigate SOI MOSFETs'. Solid-State Electronics, 51 (9):1153-1160 [Details]
(1993)'Effects of total-dose irradiation on gate-all-around (GAA) devices'
Colinge, J and Terao, Akira (1993) 'Effects of total-dose irradiation on gate-all-around (GAA) devices'. Nuclear Science, IEEE Transactions on, 40 (2):78-82 [Details]
(1982)'Stacked transistors CMOS (ST-MOS), an NMOS technology modified to CMOS'
Colinge, J and Demoulin, ERIC and Lobet, MAURICE (1982) 'Stacked transistors CMOS (ST-MOS), an NMOS technology modified to CMOS'. Solid-State Circuits, IEEE Journal of, 17 (2):215-219 [Details]
(1994)'Evidence of two-dimensional carrier confinement in thin n-channel SOI gate-all-around (GAA) devices'
Colinge, JP and Baie, X and Bayot, Vincent (1994) 'Evidence of two-dimensional carrier confinement in thin n-channel SOI gate-all-around (GAA) devices'. Electron Device Letters, IEEE, 15 (6):193-195 [Details]
(1983)'Field effect in large grain polycrystalline silicon'
Colinge, J and Morel, H and Chante, J-P (1983) 'Field effect in large grain polycrystalline silicon'. Electron Devices, IEEE Transactions on, 30 (3):197-201 [Details]
(1989)'Method for making patterned implanted buried oxide transistors and structures'
Colinge, Jean-Pierre and Kamins, Theodore I and Marcoux, Paul J and Moll, John L and Roylance, Lynn M (1989) 'Method for making patterned implanted buried oxide transistors and structures'. [Details]
(1998)'Potential and modeling of 1-$\mu$m soi cmos operational transconductance amplifiers for applications up to 1 GHz'
Eggermont, J-P and Flandre, Denis and Raskin, J-P and Colinge, J (1998) 'Potential and modeling of 1-$\mu$m soi cmos operational transconductance amplifiers for applications up to 1 GHz'. Solid-State Circuits, IEEE Journal of, 33 (4):640-643 [Details]
(2000)'Self-aligned silicon-on-insulator nano flash memory device'
Tang, Xiaohui and Baie, X and Colinge, JP and Crahay, Andr\'e and Katschmarsyj, B and Scheuren, V and Spote, David and Reckinger, Nicolas and Van de Wiele, F and Bayot, Vincent (2000) 'Self-aligned silicon-on-insulator nano flash memory device'. Solid-State Electronics, 44 (12):2259-2264 [Details]
(2010)'Junctionless 6T SRAM cell'
Kranti, A and Lee, C-W and Ferain, I and Yan, R and Akhavan, N and Razavi, P and Yu, R and Armstrong, GA and Colinge, J-P (2010) 'Junctionless 6T SRAM cell'. Electronics letters, 46 (22):1491-1493 [Details]
(2004)'Body effect in tri-and pi-gate SOI MOSFETs'
Frei, James and Johns, Chad and Vazquez, Akaena and Xiong, Weize and Cleavelin, C Rinn and Schulz, Thomas and Chaudhary, Nirmal and Gebara, Gabriel and Zaman, Jyoti R and Gostkowski, Michael and others (2004) 'Body effect in tri-and pi-gate SOI MOSFETs'. Electron Device Letters, IEEE, 25 (12):813-815 [Details]
(2011)'Cryogenic operation of junctionless nanowire transistors'
de Souza, Michelly and Pavanello, Marcelo A and Trevisoli, Renan D and Doria, Rodrigo T and Colinge, J (2011) 'Cryogenic operation of junctionless nanowire transistors'. Electron Device Letters, IEEE, 32 (10):1322-1324 [Details]
(1987)'Some properties of thin-film SOI MOSFETs'
Colinge, J-P (1987) 'Some properties of thin-film SOI MOSFETs'. Circuits and Devices Magazine, IEEE, 3 (6):16-20 [Details]
(1987)'CMOS circuits made in thin SIMOX films'
Colinge, Jean-Pierre and Kamins, TI (1987) 'CMOS circuits made in thin SIMOX films'. Electronics Letters, 23 (21):1162-1164 [Details]
(1999)'Recombination current modeling and carrier lifetime extraction in dual-gate fully-depleted SOI devices'
Ernst, Thomas and Cristoloveanu, Sorin and Vandooren, Anne and Rudenko, Tamara and Colinge, J (1999) 'Recombination current modeling and carrier lifetime extraction in dual-gate fully-depleted SOI devices'. Electron Devices, IEEE Transactions on, 46 (7):1503-1509 [Details]
(1998)'Silicon-on-lnsulator Technology: Past Achievements and Future Prospects'
Colinge, Jean-Pierre (1998) 'Silicon-on-lnsulator Technology: Past Achievements and Future Prospects'. MRS Bulletin, 23 (12):16-19 [Details]
(2008)'Sensitivity of trigate MOSFETs to random dopant induced threshold voltage fluctuations'
Yan, Ran and Lynch, Danny and Cayron, Thibault and Lederer, Dimitri and Afzalian, Aryan and Lee, Chi-Woo and Dehdashti, Nima and Colinge, JP (2008) 'Sensitivity of trigate MOSFETs to random dopant induced threshold voltage fluctuations'. Solid-State Electronics, 52 (12):1872-1876 [Details]
(2006)'Room-temperature low-dimensional effects in Pi-gate SOI MOSFETs'
Colinge, JP and Xiong, Weize and Cleavelin, CR and Schulz, T and SCHRIIFER, K and Matthews, K and Patruno, P (2006) 'Room-temperature low-dimensional effects in Pi-gate SOI MOSFETs'. IEEE electron device letters, 27 (9):775-777 [Details]
(2011)'Junctionless nanowire transistor: complementary metal-oxide-semiconductor without junctions'
Colinge, Jean-Pierre and Ferain, Isabelle and Kranti, Abhinav and Lee, Chi-Woo and Akhavan, Nima Dehdashti and Razavi, Pedram and Yan, Ran and Yu, Ran (2011) 'Junctionless nanowire transistor: complementary metal-oxide-semiconductor without junctions'. Science of Advanced Materials, 3 (3):477-482 [Details]
(2009)'A new F (ast)-CMS NEGF algorithm for efficient 3D simulations of switching characteristics enhancement in constricted tunnel barrier silicon nanowire MuGFETs'
Afzalian, Aryan and Akhavan, Nima Dehdashti and Lee, Chi-Woo and Yan, Ran and Ferain, Isabelle and Razavi, Pedram and Colinge, Jean-Pierre (2009) 'A new F (ast)-CMS NEGF algorithm for efficient 3D simulations of switching characteristics enhancement in constricted tunnel barrier silicon nanowire MuGFETs'. Journal of computational electronics, 8 (3-4):287-306 [Details]
(1995)'The development of CMOS/SIMOX technology'
Colinge, Jean-Pierre (1995) 'The development of CMOS/SIMOX technology'. Microelectronic Engineering, 28 (1):423-430 [Details]
(2006)'Radiation dose effects in trigate SOI MOS transistors'
Colinge, JP and Orozco, A and Rudee, J and Xiong, Weize and Cleavelin, C Rinn and Schulz, T and Schrufer, K and Knoblinger, G and Patruno, P (2006) 'Radiation dose effects in trigate SOI MOS transistors'. Nuclear Science, IEEE Transactions on, 53 (6):3237-3241 [Details]
(1993)'The ESD protection capability of SOI snapback nMOSFETs: Mechanisms and failure modes'
Verhaege, K and Groeseneken, G and Maes, H and Colinge, J (1993) 'The ESD protection capability of SOI snapback nMOSFETs: Mechanisms and failure modes'. ELECTRICAL OVERSTRESS ELECTROSTATIC DISCHARGE SYMPOSIUM PROCEEDINGS, :215-215 [Details]
(1990)'Model for the potential drop in the silicon substrate for thin-film SOI MOSFETs'
Martino, JA and Lauwers, L and Colinge, JP and De Meyer, K (1990) 'Model for the potential drop in the silicon substrate for thin-film SOI MOSFETs'. Electronics Letters, 26 (18):1462-1464 [Details]
(1993)'Double Snapback in SOI nMOSFET's and its Application for SOI ESD Protection'
Verhaege, Koen and Groeseneken, Guido and Colinge, J-P and Maes, Herman E (1993) 'Double Snapback in SOI nMOSFET's and its Application for SOI ESD Protection'. IEEE electron device letters, 14 (7):326-328 [Details]
(2002)'On the high-temperature subthreshold slope of thin-film SOI MOSFETs'
Rudenko, Tamara and Kilchytska, V and Colinge, J and Dessard, V and Flandre, Denis (2002) 'On the high-temperature subthreshold slope of thin-film SOI MOSFETs'. Electron Device Letters, IEEE, 23 (3):148-150 [Details]
(1999)'Self-aligned implanted ground-plane fully depleted SOI MOSFET'
Xiong, Weize and Colinge, JP (1999) 'Self-aligned implanted ground-plane fully depleted SOI MOSFET'. Electronics Letters, 35 (23):2059-2060 [Details]
(1981)'Laser light absorption in multilayers'
Colinge, JP and Van de Wiele, F (1981) 'Laser light absorption in multilayers'. Journal of Applied Physics, 52 (7):4769-4771 [Details]
(1999)'Gate-all-around OTA's for rad-hard and high-temperature analog applications'
Vandooren, A and Colinge, JP and Flandre, D (1999) 'Gate-all-around OTA's for rad-hard and high-temperature analog applications'. Nuclear Science, IEEE Transactions on, 46 (4):1242-1249 [Details]
(1995)'Temporal analysis of SEU in SOI/GAA SRAMs'
Francis, P and Colinge, JP and Berger, Guy (1995) 'Temporal analysis of SEU in SOI/GAA SRAMs'. Nuclear Science, IEEE Transactions on, 42 (6):2127-2137 [Details]
(1986)'High-speed, low-power, implanted-buried-oxide CMOS circuits'
Colinge, J and Hashimoto, K and Kamins, T and Chiang, Shang-yi and Liu, En-Den and Peng, Shiesen and Rissman, P (1986) 'High-speed, low-power, implanted-buried-oxide CMOS circuits'. Electron Device Letters, IEEE, 7 (5):279-281 [Details]
(1997)'Fully depleted SOI-CMOS technology for high temperature IC applications'
Gentinne, B and Eggermont, J-P and Flandre, Denis and Colinge, J-P (1997) 'Fully depleted SOI-CMOS technology for high temperature IC applications'. Materials Science and Engineering: B, 46 (1):1-7 [Details]
(1988)'Process for the production of mutually electrically insulated monocrystalline silicon islands using laser recrystallization'
Bensahel, Daniel and Colinge, Jean-Pierre and Dutartre, Didier and Haond, Michel and others (1988) 'Process for the production of mutually electrically insulated monocrystalline silicon islands using laser recrystallization'. [Details]
(2008)'Ultra-scaled Z-RAM cell'
Okhonin, S and Nagoga, M and Lee, Chi-Woo and Colinge, Jean-Pierre and Afzalian, Aryan and Yan, Ran and Akhavan, N Dehdashti and Xiong, Weize and Sverdlov, Viktor and Selberherr, Siegfried and others (2008) 'Ultra-scaled Z-RAM cell'. Proc. IEEE Int. SOI Conf, :157-158 [Details]
(1988)'Thin-film, accumulation-mode p-channel SOI MOSFETs'
Colinge, JP (1988) 'Thin-film, accumulation-mode p-channel SOI MOSFETs'. Electronics Letters, 24 (5):257-258 [Details]
(1998)'Silicon-on-lnsulator Technology'
Colinge, Jean-Pierre and Bower, Robert W (1998) 'Silicon-on-lnsulator Technology'. MRS Bulletin, 23 (12):13-15 [Details]
(1998)'Two-dimensional confinement effects in gate-all-around (GAA) MOSFETs'
Baie, X and Colinge, JP (1998) 'Two-dimensional confinement effects in gate-all-around (GAA) MOSFETs'. Solid-State Electronics, 42 (4):499-504 [Details]
(1997)'Electrical properties and radiation hardness of SOI systems with multilayer buried dielectric'
Barchuk, IP and Kilchitskaya, VI and Lysenko, VS and Nazarov, AN and Rudenko, TE and Djurenko, SV and Rudenko, AN and Yurchenko, AP and Ballutaud, D and Colinge, JP (1997) 'Electrical properties and radiation hardness of SOI systems with multilayer buried dielectric'. Nuclear Science, IEEE Transactions on, 44 (6):2542-2552 [Details]
(1993)'Evidence of different conduction mechanisms in accumulation-mode p-channel SOI MOSFET's at room and liquid-helium temperatures'
Rotondaro, Antonio Luis Pacheco and Magnusson, Ulf K and Claeys, Cor and Flandre, D and Terao, A and Colinge, JP (1993) 'Evidence of different conduction mechanisms in accumulation-mode p-channel SOI MOSFET's at room and liquid-helium temperatures'. Electron Devices, IEEE Transactions on, 40 (4):727-732 [Details]
(2010)'Short-channel junctionless nanowire transistors'
Lee, CW and Ferain, I and Kranti, A and Akhavan, N Dehdashti and Razavi, P and Yan, R and Yu, R and O’Neill, B and Blake, A and White, M and others (2010) 'Short-channel junctionless nanowire transistors'. Proc. SSDM, :1044-1045 [Details]
(1985)'Transconductance of Silicon-on-insulator (SOI) MOSFET's'
Colinge, J (1985) 'Transconductance of Silicon-on-insulator (SOI) MOSFET's'. Electron Device Letters, IEEE, 6 (11):573-574 [Details]
(2006)'Dose radiation effects in FinFETs'
Wu, Xusheng and Chan, Philip CH and Orozco, A and Vazquez, A and Chaudhry, A and Colinge, JP (2006) 'Dose radiation effects in FinFETs'. Solid-state electronics, 50 (2):287-290 [Details]
(2011)'Improvement of carrier ballisticity in junctionless nanowire transistors'
Akhavan, Nima Dehdashti and Ferain, Isabelle and Razavi, Pedram and Yu, Ran and Colinge, Jean-Pierre (2011) 'Improvement of carrier ballisticity in junctionless nanowire transistors'. Applied Physics Letters, 98 (10) [Details]
(2010)'Low-temperature conductance oscillations in junctionless nanowire transistors'
Park, Jong-Tae and Kim, Jin Young and Lee, Chi-Woo and Colinge, Jean-Pierre (2010) 'Low-temperature conductance oscillations in junctionless nanowire transistors'. Applied Physics Letters, 97 (17) [Details]
(2010)'Mobility improvement in nanowire junctionless transistors by uniaxial strain'
Raskin, Jean-Pierre and Colinge, Jean-Pierre and Ferain, Isabelle and Kranti, Abhinav and Lee, Chi-Woo and Akhavan, Nima Dehdashti and Yan, Ran and Razavi, Pedram and Yu, Ran (2010) 'Mobility improvement in nanowire junctionless transistors by uniaxial strain'. Applied Physics Letters, 97 (4) [Details]
(2011)'Low-frequency noise in junctionless multigate transistors'
Jang, Doyoung and Lee, Jae Woo and Lee, Chi-Woo and Colinge, Jean-Pierre and Mont\`es, Laurent and Lee, Jung Il and Kim, Gyu Tae and Ghibaudo, G\'erard (2011) 'Low-frequency noise in junctionless multigate transistors'. Applied Physics Letters, 98 (13) [Details]
(1989)'Analysis of drain breakdown voltage in SOI n-channel MOSFETs'
Haond, M and Colinge, JP (1989) 'Analysis of drain breakdown voltage in SOI n-channel MOSFETs'. Electronics Letters, 25 (24):1640-1641 [Details]
(2005)'Full/partial depletion effects in FinFETs'
Xiong, W and Cleavelin, C Rinn and Wise, Rick and Yu, SHAOFENG and Pas, Michael and Zaman, RJ and Gostkowski, Michael and Matthews, Kenneth and Maleville, C and Patruno, Paul and others (2005) 'Full/partial depletion effects in FinFETs'. Electronics Letters, 41 (8):504-506 [Details]
(1986)'Thickness determination for silicon-on-insulator structures'
Kamins, TI and Colinge, JP (1986) 'Thickness determination for silicon-on-insulator structures'. Electronics Letters, 22 (23):1236-1237 [Details]
(1988)'Bulk traps in ultrathin SIMOX MOSFET's by current DLTS'
McLarty, Peter K and Ioannou, Dimitris E and Colinge, J (1988) 'Bulk traps in ultrathin SIMOX MOSFET's by current DLTS'. Electron Device Letters, IEEE, 9 (10):545-547 [Details]
(1986)'Half-micrometre-base lateral bipolar transistors made in thin silicon-on-insulator films'
Colinge, JP (1986) 'Half-micrometre-base lateral bipolar transistors made in thin silicon-on-insulator films'. Electronics letters, 22 (17):886-887 [Details]
(2008)'The new generation of SOI MOSFETs'
Colinge, JP (2008) 'The new generation of SOI MOSFETs'. Romaniam Journal Information Science and Technology, 11 (1):3-15 [Details]
(1997)'Substrate influences on fully depleted enhancement mode SOI MOSFETs at room temperature and at 77 K'
Pavanello, Marcelo Antonio and Martino, Jo\~ao Antonio and Colinge, Jean-Pierre (1997) 'Substrate influences on fully depleted enhancement mode SOI MOSFETs at room temperature and at 77 K'. Solid-State Electronics, 41 (1):111-119 [Details]
(2004)'Improvement of FinFET electrical characteristics by hydrogen annealing'
Xiong, Weize and Gebara, Gabriel and Zaman, Joyti and Gostkowski, Michael and Nguyen, Billy and Smith, Greg and Lewis, David and Cleavelin, C Rinn and Wise, Rick and Yu, Shaofeng and others (2004) 'Improvement of FinFET electrical characteristics by hydrogen annealing'. Electron Device Letters, IEEE, 25 (8):541-543 [Details]
(2010)'Reduced electric field in junctionless transistors'
Colinge, Jean-Pierre and Lee, Chi-Woo and Ferain, Isabelle and Akhavan, Nima Dehdashti and Yan, Ran and Razavi, Pedram and Yu, Ran and Nazarov, Alexei N and Doria, Rodrigo T (2010) 'Reduced electric field in junctionless transistors'. Applied Physics Letters, 96 (7) [Details]
(1998)'Fully-depleted SOI CMOS for analog applications'
Colinge, J (1998) 'Fully-depleted SOI CMOS for analog applications'. Electron Devices, IEEE Transactions on, 45 (5):1010-1016 [Details]
(1997)'SOI technology: materials to VLSI'
Colinge, Jean-Pierre (1997) 'SOI technology: materials to VLSI'. Kluwer, Boston, [Details]
(1998)'Accurate SOI MOSFET characterization at microwave frequencies for device performance optimization and analog modeling'
Raskin, J-P and Gillon, Renaud and Chen, Jian and Vanhoenacker-Janvier, Danielle and Colinge, J (1998) 'Accurate SOI MOSFET characterization at microwave frequencies for device performance optimization and analog modeling'. Electron Devices, IEEE Transactions on, 45 (5):1017-1025 [Details]
(1990)'Temperature dependence of threshold voltage in thin-film SOI MOSFETs'
Groeseneken, Guido and Colinge, JP and Maes, Herman E and Alderman, JC and Holt, S (1990) 'Temperature dependence of threshold voltage in thin-film SOI MOSFETs'. Electron Device Letters, IEEE, 11 (8):329-331 [Details]
(1990)'Subthreshold slope in thin-film SOI MOSFETs'
Wouters, Dirk J and Colinge, J and Maes, Herman E (1990) 'Subthreshold slope in thin-film SOI MOSFETs'. Electron Devices, IEEE Transactions on, 37 (9):2022-2033 [Details]
(1988)'Increased drain saturation current in ultra-thin silicon-on-insulator (SOI) MOS transistors'
Sturm, James C and Tokunaga, K and Colinge, J (1988) 'Increased drain saturation current in ultra-thin silicon-on-insulator (SOI) MOS transistors'. Electron Device Letters, IEEE, 9 (9):460-463 [Details]
(2007)'Intrinsic advantages of SOI multiple-gate MOSFET (MuGFET) for low power applications'
Xiong, Weize W and Cleavelin, C Rinn and Hsu, Che-Hua and Ma, Mike and Schruefer, Klaus and Von Arnim, Klaus and Schulz, Thomas and Cayrefourcq, Ian and Mazure, Carlos and Patruno, Paul and others (2007) 'Intrinsic advantages of SOI multiple-gate MOSFET (MuGFET) for low power applications'. ECS Transactions, 6 (4):59-69 [Details]
(2009)'Properties of accumulation-mode multi-gate field-effect transistors'
Colinge, Jean-Pierre and Lederer, Dimitri and Afzalian, Aryan and Yan, Ran and Lee, Chi-Woo and Akhavan, Nima Dehdashti and Xiong, Weize (2009) 'Properties of accumulation-mode multi-gate field-effect transistors'. Japanese Journal of Applied Physics, 48 (3R) [Details]
(2010)'Simulation of quantum current oscillations in trigate SOI MOSFETs'
Akhavan, Nima Dehdashti and Afzalian, Aryan and Lee, Chi-Woo and Yan, Ran and Ferain, Isabelle and Razavi, Pedram and Fagas, Giorgos and Colinge, J (2010) 'Simulation of quantum current oscillations in trigate SOI MOSFETs'. Electron Devices, IEEE Transactions on, 57 (5):1102-1109 [Details]
(1993)'Metastable charge-trapping effect in SOI nMOSTs at 4.2 K'
Simoen, E and Gao, M-H and Colinge, J-P and Claeys, Cor (1993) 'Metastable charge-trapping effect in SOI nMOSTs at 4.2 K'. Semiconductor science and technology, 8 (3) [Details]
(2004)'Determination of film and surface recombination in thin-film SOI devices using gated-diode technique'
Rudenko, Tamara and Rudenko, A and Kilchytska, V and Cristoloveanu, S and Ernst, T and Colinge, J-P and Dessard, V and Flandre, D (2004) 'Determination of film and surface recombination in thin-film SOI devices using gated-diode technique'. Solid-State Electronics, 48 (3):389-399 [Details]
(2011)'Random telegraph-signal noise in junctionless transistors'
Nazarov, AN and Ferain, I and Akhavan, N Dehdashti and Razavi, P and Yu, R and Colinge, JP (2011) 'Random telegraph-signal noise in junctionless transistors'. Applied Physics Letters, 98 (9) [Details]
(1989)'Bipolar transistor process using sidewall spacer for aligning base insert'
Colinge, Jean-Pierre (1989) 'Bipolar transistor process using sidewall spacer for aligning base insert'. [Details]
(2003)'Application of the EKV model to the DTMOS SOI transistor'
Colinge, Jean-Pierre and Park, Jong-Tae (2003) 'Application of the EKV model to the DTMOS SOI transistor'. journal of semiconductor technology and science, 3 (4) [Details]
(2012)'Mobility and screening effect in heavily doped accumulation-mode metal-oxide-semiconductor field-effect transistors'
Goto, Ken-Ichi and Yu, Tsung-Hsing and Wu, Jeff and Diaz, Carlos H and Colinge, JP (2012) 'Mobility and screening effect in heavily doped accumulation-mode metal-oxide-semiconductor field-effect transistors'. Applied Physics Letters, 101 (7) [Details]
(2008)'Comparison of contact resistance between accumulation-mode and inversion-mode multigate FETs'
Lee, Chi-Woo and Lederer, Dimitri and Afzalian, Aryan and Yan, Ran and Dehdashti, Nima and Xiong, Weize and Colinge, Jean-Pierre (2008) 'Comparison of contact resistance between accumulation-mode and inversion-mode multigate FETs'. Solid-State Electronics, 52 (11):1815-1820 [Details]
(1995)'Performances of SOI CMOS OTA combining ZTC and gain-boosting techniques'
Gentinne, B and Eggermont, JP and Colinge, JP (1995) 'Performances of SOI CMOS OTA combining ZTC and gain-boosting techniques'. Electronics Letters, 31 (24):2092-2093 [Details]
(2009)'Direct protein detection with a nano-interdigitated array gate MOSFET'
Tang, Xiaohui and Jonas, Alain M and Nysten, Bernard and Demoustier-Champagne, Sophie and Blondeau, Franoise and Pr\'evot, Pierre-Paul and Pampin, R\'emi and Godfroid, Edmond and I\~niguez, Benjamin and Colinge, Jean-Pierre and others (2009) 'Direct protein detection with a nano-interdigitated array gate MOSFET'. Biosensors and Bioelectronics, 24 (12):3531-3537 [Details]

Conference Publications

 YearPublication
(2008)Proceeding 4th EuroSOI Workshop
A. Nazarov, V. Lysenko, D. Flandre and J.P. Colinge (2008) Hydrogen as Source of High-Temperature Charge Instability in the Buried Oxide of SOI Structures and MOSFETs Proceeding 4th EuroSOI Workshop [Details]
(1990)Electron Devices Meeting, 1990. IEDM'90. Technical Digest., International
Colinge, Jean-Pierre and Gao, MH and Romano-Rodriguez, A and Maes, H and Claeys, C (1990) Silicon-on-insulator'gate-all-around device' Electron Devices Meeting, 1990. IEDM'90. Technical Digest., International , pp.595-598 [Details]
(2003)SOI Conference, 2003. IEEE International
Xiong, Weize and Park, JW and Colinge, JP (2003) Corner effect in multiple-gate SOI MOSFETs SOI Conference, 2003. IEEE International , pp.111-113 [Details]
(2010)Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European
Kranti, A and Yan, R and Lee, C-W and Ferain, I and Yu, R and Dehdashti Akhavan, N and Razavi, P and Colinge, JP (2010) Junctionless nanowire transistor (JNT): properties and design guidelines Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European , pp.357-360 [Details]
(2000)Microelectronics, 2000. Proceedings. 2000 22nd International Conference on
Colinge, J-P (2000) SOI devices and circuits Microelectronics, 2000. Proceedings. 2000 22nd International Conference on , pp.407-414 [Details]
(2004)SOI Conference, 2004. Proceedings. 2004 IEEE International
Colinge, JP (2004) SOI for hostile environment applications SOI Conference, 2004. Proceedings. 2004 IEEE International , pp.1-4 [Details]
(2003)SOI Conference, 2003. IEEE International
Park, JW and Xiong, W and Colinge, JP (2003) Accumulation-mode pi-gate MOSFET SOI Conference, 2003. IEEE International , pp.65-67 [Details]
(2010)Nanotechnology (IEEE-NANO), 2010 10th IEEE Conference on
Lee, Chi-Woo and Yan, Ran and Ferain, Isabelle and Kranti, Abhinav and Akhvan, ND and Razavi, Pedram and Yu, Ran and Colinge, JP (2010) Nanowire zero-capacitor DRAM transistors with and without junctions Nanotechnology (IEEE-NANO), 2010 10th IEEE Conference on , pp.242-245 [Details]
(2011)SOI Conference (SOI), 2011 IEEE International
Akhavan, Nima Dehdashti and Ferain, Isabelle and Razavi, Pedram and Yu, Ran and Colinge, J (2011) Random dopant variation in junctionless nanowire transistors SOI Conference (SOI), 2011 IEEE International , pp.1-2 [Details]
(1995)IEEE International SOI Conference, 1995
Gentinne, Bernard and Dessard, Vincent and Louveaux, S and Flandre, Denis and Colinge, Jean-Pierre and others (1995) A comparative study of non-linearities in bulk and SOI linear resistors based on 2-and 4-transistor structures IEEE International SOI Conference, 1995 [Details]
(1991)SOI Conference, 1991. Proceedings, 1991., IEEE International
Lawrence, RK and Colinge, JP and Hughes, HL (1991) Radiation effects in gate-all-around structures SOI Conference, 1991. Proceedings, 1991., IEEE International , pp.80-81 [Details]
(2007)SOI Conference, 2007 IEEE International
Patruno, Paul and Kostrzewa, Marek and Landry, K and Xiong, Weize and Cleavelin, CR and Hsu, Che-Hua and Ma, M and Colinge, J (2007) Study of Fin Profiles and MuGFETs built on SOI Wafers with a Nitride-Oxide Buried Layer (NOx-BL) as the Buried Insulator Layer SOI Conference, 2007 IEEE International , pp.51-52 [Details]
(1992)SOI Conference, 1992. IEEE International
Gentinne, B and Colinge, JP and Jespers, PGA (1992) Performances of fully-depleted SOI analog operational amplifiers SOI Conference, 1992. IEEE International , pp.162-163 [Details]
(1997)International conference on microelectronic
Colinge, J-P (1997) Performances of low-voltage, low-power SOI CMOS technology International conference on microelectronic , pp.229-236 [Details]
(1999)SOI Conference, 1999. Proceedings. 1999 IEEE International
Tang, Xiaohui and Baie, Xavier and Bayot, Vincent and Van de Wiele, Fernand and Colinge, Jean-Pierre (1999) An SOI single-electron transistor SOI Conference, 1999. Proceedings. 1999 IEEE International , pp.46-47 [Details]
(2007)SOI Conference, 2007 IEEE International
Yun, Se Re Na and Yu, Chong Gun and Park, Jong Tae and Lee, Chi-Woo and Lederer, Dimitri and Afzalian, Aryan and Yan, Ran and Colinge, Jean-Pierre (2007) A quantum definition of threshold voltage in MuGFETs SOI Conference, 2007 IEEE International , pp.137-138 [Details]
(2000)SOI Conference, 2000 IEEE International
Vandooren, A and Cristoloveanu, S and Colinge, JP (2000) The dynamic conductance and transconductance in double-gate (gate-all-round) SOI devices SOI Conference, 2000 IEEE International , pp.116-117 [Details]
(1997)SOI Conference, 1997. Proceedings., 1997 IEEE International
Raskin, Jean-Pierre and Eggermont, J-P and Vanhoenacker, D and Colinge, Jean-Pierre (1997) Synthetic microwave inductors in SOI technology SOI Conference, 1997. Proceedings., 1997 IEEE International , pp.90-91 [Details]
(1995)SOI Conference, 1995. Proceedings., 1995 IEEE International
Eggermont, J-P and Flandre, Denis and Gillon, Renaud and Colinge, Jean-Pierre (1995) A 1-GHz operational transconductance amplifier in SOI technology SOI Conference, 1995. Proceedings., 1995 IEEE International , pp.127-128 [Details]
(2003)Semiconductor Device Research Symposium, 2003 International
Colinge, J-P (2003) The evolution of silicon-on-insulator MOSFETs Semiconductor Device Research Symposium, 2003 International , pp.354-355 [Details]
(1992)IEEE International SOI Conference, 1992
Flandre, Denis and Jacquemin, C and Colinge, Jean-Pierre and others (1992) Design techniques for high-speed low-power and high-temperature digital CMOS circuits on SOI IEEE International SOI Conference, 1992 [Details]
(2008)IEEE 2008 Silicon Nanoelectronics Workshop
Afzalian, Aryan and Lederer, Dimitri and Lee, Chi-Woo and Yan, Ran and Xiong, Weize and Cleavelin, C Rinn and Colinge, Jean-Pierre and others (2008) MultiGate SOI MOSFETs: accumulation-mode vs. enhancement-mode IEEE 2008 Silicon Nanoelectronics Workshop [Details]
(1991)SOI Conference, 1991. Proceedings, 1991., IEEE International
Colinge, J (1991) Problems and issues in SOI CMOS technology SOI Conference, 1991. Proceedings, 1991., IEEE International , pp.126-127 [Details]
(2009)2009 IEEE International SOI Conference
Yan, Ran and Duane, R and Razavi, P and Afzalian, Aryan and Ferain, Isabelle and Lee, Chi-Woo and Dehdashti-Akhavan, Nima and Bourdelle, K and Nguyen, BY and Colinge, Jean-Pierre and others (2009) LDD depletion effects in thin-BOX FDSOI devices with a ground plane 2009 IEEE International SOI Conference [Details]
(1991)SOI Conference, 1991. Proceedings, 1991., IEEE International
Gao, MH and Wu, S-H and Colinge, JP and Claeys, C and Declerck, G (1991) Single device inverter using SOI cross-MOSFET's SOI Conference, 1991. Proceedings, 1991., IEEE International , pp.138-139 [Details]
(1996)SOI Conference, 1996. Proceedings., 1996 IEEE International
Raskin, Jean-Pierre and Huynen, Isabelle and Gillon, Renaud and Vanhoenacker, D and Colinge, Jean-Pierre (1996) An efficient design tool for transmission line on SIMOX substrates SOI Conference, 1996. Proceedings., 1996 IEEE International , pp.28-29 [Details]
(2000)SOI Conference, 2000 IEEE International
Rudenko, Tamara and Kilchytska, Valeriya and Colinge, Jean-Pierre and Flandre, Denis (2000) Physical analysis of the high-temperature subthreshold slope in SOI MOSFETs SOI Conference, 2000 IEEE International , pp.34-35 [Details]
(1993)SOI Conference, 1993. Proceedings., 1993 IEEE International
Flandre, D and Francis, P and Colinge, JP and Cristoloveanu, S (1993) Comparison of hot-carrier effects in thin-film SOI and gate-all-around accumulation-mode p-MOSFETs SOI Conference, 1993. Proceedings., 1993 IEEE International , pp.160-161 [Details]
(2010)Simulation of Semiconductor Processes and Devices (SISPAD), 2010 International Conference on
Dehdashti, Nima and Kranti, Abhinav and Ferain, Isabelle and Lee, Chi-Woo and Yan, Ran and Razavi, Pedram and Yu, Ran and Colinge, J (2010) Dissipative transport in multigate silicon nanowire transistors Simulation of Semiconductor Processes and Devices (SISPAD), 2010 International Conference on , pp.97-100 [Details]
(2012)Future of Electron Devices, Kansai (IMFEDK), 2012 IEEE International Meeting for
Colinge, J-P (2012) Junctionless transistors Future of Electron Devices, Kansai (IMFEDK), 2012 IEEE International Meeting for , pp.1-2 [Details]
(1998)SOI Conference, 1998. Proceedings., 1998 IEEE International
Ernst, T and Cristoloveanu, S and Vandooren, A and Colinge, JP and Rudenko, T (1998) Carrier lifetime extraction in fully-depleted SOI devices SOI Conference, 1998. Proceedings., 1998 IEEE International , pp.21-22 [Details]
(1992)IEEE International SOI Conference, 1992
Gentinne, Bernard and Flandre, Denis and Terao, Akira and Colinge, Jean-Pierre and others (1992) Intrinsic gate capacitances and large-signal transient modeling of thin-film accumulation-mode p-channel SOI MOSFETs IEEE International SOI Conference, 1992 [Details]
(1995)Microwave Conference, 1995. 25th European
Gillon, Renaud and Raskin, J-P and Vanhoenacker, D and Colinge, J-P (1995) Modelling and optimising the SOI MOSFET in view of MMIC applications Microwave Conference, 1995. 25th European , pp.543-547 [Details]
(1997)SOI Conference, 1997. Proceedings., 1997 IEEE International
Colinge, JP and Cao, M and Greene, W (1997) Analog parameters of short-channel SOI MOSFETs SOI Conference, 1997. Proceedings., 1997 IEEE International , pp.88-89 [Details]
(2010)SOI Conference (SOI), 2010 IEEE International
Doria, RT and Pavanello, MA and Trevisoli, RD and de Souza, M and Lee, C-W and Ferain, I and Dehdashti Akhavan, N and Yan, R and Razavi, P and Yu, R and others (2010) Analog operation of junctionless transistors at cryogenic temperatures SOI Conference (SOI), 2010 IEEE International , pp.1-2 [Details]
(1990)SOS/SOI Technology Conference, 1990., 1990 IEEE
Gao, MH and Colinge, JP and Lauwers, L and Wu, S-H and Claeys, C (1990) Dual-MOSFET structure for suppression of kink in SOI MOSFETs at room and liquid helium temperatures SOS/SOI Technology Conference, 1990., 1990 IEEE , pp.13-14 [Details]
(2011)SOI Conference (SOI), 2011 IEEE International
Doria, RT and Trevisoli, RD and de Souza, M and Colinge, JP and Pavanello, MA (2011) Analysis of the low-frequency noise of junctionless nanowire transistors operating in saturation SOI Conference (SOI), 2011 IEEE International , pp.1-2 [Details]
(1997)SOI Conference, 1997. Proceedings., 1997 IEEE International
Vandooren, Anne and Francis, Pascale and Flandre, Denis and Colinge, Jean-Pierre (1997) Performance of $\gamma$-irradiated gate-all-around SOI MOS OTA amplifiers SOI Conference, 1997. Proceedings., 1997 IEEE International , pp.62-63 [Details]
(2010)2010 EUROSOI Conference
Afzalian, Aryan and Colinge, Jean-Pierre and Flandre, Denis and others (2010) Variable Barrier Resonant Tunneling Transistor: A New Path Towards Steep Slope and High On-Current? 2010 EUROSOI Conference [Details]
(1996)Microelectronic Test Structures, 1996. ICMTS 1996. Proceedings. 1996 IEEE International Conference on
Raskin, Jean-Pierre and Gillon, Renaud and Vanhoenacker, D and Colinge, Jean-Pierre (1996) Direct extraction method of SOI MOSFET transistors parameters Microelectronic Test Structures, 1996. ICMTS 1996. Proceedings. 1996 IEEE International Conference on , pp.191-194 [Details]
(1982)Electron Devices Meeting, 1982 International
Colinge, JP and Demoulin, E and Morel, H (1982) Field-effect in large grain polysilicon transistors Electron Devices Meeting, 1982 International , pp.444-447 [Details]
(1998)High Temperature Electronics Conference, 1998. HITEC. 1998 Fourth International
Nazarov, AN and Barchuk, IP and Colinge, JP (1998) The nature of high-temperature instability in fully depleted SOI IM n-MOSFETs High Temperature Electronics Conference, 1998. HITEC. 1998 Fourth International , pp.226-229 [Details]
(1998)SOI Conference, 1998. Proceedings., 1998 IEEE International
Vandooren, Anne and Flandre, Denis and Cristoloveanu, Sorin and Colinge, Jean-Pierre (1998) EDGE effects characterization in gate-all-around SOI MOSFETS SOI Conference, 1998. Proceedings., 1998 IEEE International , pp.75-76 [Details]
(2000)IEEE International Electron Devices Meeting (IEDM 1999)
Tang, Xiaohui and Baie, Xavier and Bayot, Vincent and Van de Wiele, Fernand and Colinge, Jean-Pierre and others (2000) Fabrication, characterization and self-consistent simulation of SOI nano flash memory device IEEE International Electron Devices Meeting (IEDM 1999) [Details]
(1997)Microwave Conference, 1997. 27th European
Huynen, Isabelle and Raskin, Jean-Pierre and Gillon, Renaud and Vanhoenacker, D and Colinge, Jean-Pierre (1997) Integrated microwave inductors on Silicon-on-Insulator substrate Microwave Conference, 1997. 27th European , pp.1008-1013 [Details]
(1994)Solid-State Circuits Conference, 1994. ESSCIRC'94. Twentieth European
Flandre, Denis and Colinge, J (1994) Status and Trends of SOI Solid-State Circuits Conference, 1994. ESSCIRC'94. Twentieth European , pp.18-27 [Details]
(1994)SOI Conference, 1994 Proceedings., 1994 IEEE International
Zaleski, A and Ioannou, DE and Flandre, Denis and Colinge, Jean-Pierre (1994) Design and performance of a new Flash EEPROM on SOI (SIMOX) substrates SOI Conference, 1994 Proceedings., 1994 IEEE International , pp.13-14 [Details]
(1996)Third International High Temperature Conference
Eggermont, Jean-Pierre and Flandre, Denis and Colinge, Jean-Pierre and others (1996) CMOS SOI magnetic field sensors for applications up to 300 C Third International High Temperature Conference [Details]
(2009)Solid State Device Research Conference, 2009. ESSDERC'09. Proceedings of the European
Lee, C-W and Ferain, Isabelle and Afzalian, Aryan and Byun, K-Y and Yan, Ran and Dehdashti, Nima and Razavi, P and Xiong, Weize and Colinge, Jean-Pierre and Colinge, CA and others (2009) Hot carrier (HC) and bias-temperature-instability (BTI) degradation of MuGFETs on silicon oxide and silicon nitride buried layers Solid State Device Research Conference, 2009. ESSDERC'09. Proceedings of the European , pp.261-264 [Details]
(1993)SOI Conference, 1993. Proceedings., 1993 IEEE International
Colinge, Jean-Pierre and Van de Wiele, F and Flandre, D (1993) Subthreshold slope of accumulation-mode p-channel SOI MOSFETs SOI Conference, 1993. Proceedings., 1993 IEEE International , pp.146-147 [Details]
(2012)Ultimate Integration on Silicon (ULIS), 2012 13th International Conference on
Yu, Ran and Das, Samaresh and Hobbs, Richard and Georgiev, Yordan and Ferain, Isabelle and Razavi, Pedram and Akhavan, Nima Dehdashti and Colinge, Cynthia A and Colinge, J (2012) Top-down process of Germanium nanowires using EBL exposure of Hydrogen Silsesquioxane resist Ultimate Integration on Silicon (ULIS), 2012 13th International Conference on , pp.145-148 [Details]
(2010)2010 International Conference on Solid State Devices and Materials-SSDM 2010
Colinge, Jean-Pierre and Raskin, Jean-Pierre and Ferain, I and Kranti, A and others (2010) Analysis of the Junctionless Transistor Architecture 2010 International Conference on Solid State Devices and Materials-SSDM 2010 [Details]
(1996)Third International High Temperature Conference
Gentinne, Bernard and Flandre, Denis and Eggermont, Jean-Pierre and Colinge, Jean-Pierre and others (1996) High-temperature performances of a SOI CMOS gain-boosting OTA Third International High Temperature Conference [Details]
(2009)SISPAD 2009
Afzalian, Aryan and Lee, Chi-Woo and Dehdashti-Akhavan, Nima and Yan, Ran and Ferain, Isabelle and Colinge, Jean-Pierre and others (2009) A new F (ast)-CMS Algorithm for Efficient Three-Dimensional NEGF Simulations of Arbitrary Shaped Silicon Nanowire MUGFETs SISPAD 2009 [Details]
(1997)48th Electrochemical Society Meeting-SOI symposium
Gillon, Renaud and Raskin, Jean-Pierre and Vanhoenacker-Janvier, Danielle and Colinge, Jean-Pierre and Dambrine, G and others (1997) Characterization of SOI MOSFETs at microwave frequencies 48th Electrochemical Society Meeting-SOI symposium [Details]
(1996)Solid State Device Research Conference, 1996. ESSDERC'96. Proceedings of the 26th European
Colinge, Jean-Pierre (1996) Recent advances and trends in SOI CMOS technology Solid State Device Research Conference, 1996. ESSDERC'96. Proceedings of the 26th European , pp.935-942 [Details]
(2007)SOI Conference, 2007 IEEE International
Xiong, W and Cleavelin, CR and Hsu, CH and Ma, M and Schulz, T and Schruefer, K and Patruno, P and Colinge, JP (2007) Multi-Gate SOI MOSFET Operations in Harsh Environments SOI Conference, 2007 IEEE International , pp.29-30 [Details]
(2013)Custom Integrated Circuits Conference (CICC), 2013 IEEE
Colinge, Jean-Pierre and Dhong, Sang H (2013) Prospective for nanowire transistors Custom Integrated Circuits Conference (CICC), 2013 IEEE , pp.1-8 [Details]
(2012)Ultimate Integration on Silicon (ULIS), 2012 13th International Conference on
Razavi, Pedram and Ferain, Isabelle and Das, Samaresh and Yu, Ran and Akhavan, Nima Dehdashti and Colinge, J (2012) Intrinsic gate delay and energy-delay product in junctionless nanowire transistors Ultimate Integration on Silicon (ULIS), 2012 13th International Conference on , pp.125-128 [Details]
(2007)2007 IEEE International SOI Conference
Xiong, Weize and Hsu, CH and Cleavelin, CR and Ma, M and Patruno, P and Lee, Chi-Woo and Yan, Ran and Lederer, Dimitri and Afzalian, Aryan and Colinge, Jean-Pierre and others (2007) Influence of Fluorine Implant on Threshold Voltage for Metal Gate FDSOI and MuGFET 2007 IEEE International SOI Conference [Details]
(2010)2010 SemOI Conference
Afzalian, Aryan and Colinge, Jean-Pierre and Flandre, Denis and others (2010) Variable barrier resonant tunneling transistor: performance investigation of a steep slope, high on-current device 2010 SemOI Conference [Details]
(2009)Simulation of Semiconductor Processes and Devices, 2009. SISPAD'09. International Conference on
Afzalian, A and Lee, C-W and Dehdashti Akhavan, N and Yan, R and Ferain, I and Razavi, P and Colinge, JP (2009) A new F (ast)-CMS Algorithm for Efficient Three-Dimensional NEGF Simulations of Arbitrarily Shaped Silicon Nanowire MUGFETs Simulation of Semiconductor Processes and Devices, 2009. SISPAD'09. International Conference on , pp.1-4 [Details]
(1999)High Temperature Electronics, 1999. HITEN 99. The Third European Conference on
Rudenko, Tamara and Lysenko, V and Rudenko, A and Kilchytska, V and Colinge, Jean-Pierre (1999) A study on the high-temperature subthreshold slope in SOI MOSFETs High Temperature Electronics, 1999. HITEN 99. The Third European Conference on , pp.53-56 [Details]
(1989)SOS/SOI Technology Conference, 1989., 1989 IEEE
Wouters, DJ and Colinge, J-P and Maes, HE (1989) Subthreshold current in thick and thin-film SOI MOSFET transistors SOS/SOI Technology Conference, 1989., 1989 IEEE , pp.21-22 [Details]
(2000)SOI Conference, 2000 IEEE International
Vandooren, A and Cristoloveanu, S and Colinge, JP (2000) Hall mobility measurement in double-gate SOI MOSFETs SOI Conference, 2000 IEEE International , pp.118-119 [Details]
(2008)2008 China-Ireland International Conference on Information and Communication Technologies (CIICT 2008)
Yan, Ran and Afzalian, Aryan and Lee, Chi-Woo and Dehdashti Akhavan, Nima and Xiong, Weize and Colinge, Jean-Pierre and others (2008) 3D simulation and measurement of very narrow AM and IM triple-gate MOSFETs 2008 China-Ireland International Conference on Information and Communication Technologies (CIICT 2008) [Details]
(2009)SOI Conference, 2009 IEEE International
Afzalian, Aryan and Dehdashti, Nima and Ferain, Isabelle and Lee, C-W and Yan, Ran and Razavi, P and Colinge, Jean-Pierre (2009) Variable-barrier tunneling SOI transistor (VBT) SOI Conference, 2009 IEEE International , pp.1-2 [Details]
(1999)Third European Conference on High Temperature Electronics (HITEN 1999)
Rudenko, Tamara and Lysenko, V and Kilchytska, Valeriya and Rudenko, A and Colinge, Jean-Pierre and others (1999) Properties of high-temperature off-state currents in SOI MOSFETs derived from the diffusion mechanism Third European Conference on High Temperature Electronics (HITEN 1999) [Details]
(2011)Ultimate Integration on Silicon (ULIS), 2011 12th International Conference on
Ansari, Lida and Feldman, Baruch and Fagas, Giorgos and Colinge, J and Greer, James C (2011) Atomic scale simulation of a junctionless silicon nanowire transistor Ultimate Integration on Silicon (ULIS), 2011 12th International Conference on , pp.1-3 [Details]
(2009)Computational Electronics, 2009. IWCE'09. 13th International Workshop on
Dehdashti, Nima and Afzalian, A and Lee, C-W and Yan, R and Fagas, G and Colinge, JP (2009) Device characteristics of Trigate-FET with barrier constrictions in the channel Computational Electronics, 2009. IWCE'09. 13th International Workshop on , pp.1-4 [Details]
(1993)SOI Conference, 1993. Proceedings., 1993 IEEE International
Gentinne, B and Colinge, JP and Jespers, PGA and Eggermont, J-P (1993) Improvement of the performances of SOI CMOS operational amplifiers by means of a gain-boosting stage SOI Conference, 1993. Proceedings., 1993 IEEE International , pp.184-185 [Details]
(1989)SOS/SOI Technology Conference, 1989., 1989 IEEE
Colinge, J-P and Tack, M (1989) On the optimization of silicon film thickness in thin-film SOI devices SOS/SOI Technology Conference, 1989., 1989 IEEE , pp.13-14 [Details]
(1990)Solid State Device Research Conference, 1990. ESSDERC'90. 20th European
Gao, MH and Colinge, J-P and Wu, S-H and Claeys, C (1990) Improvement of output impedance in SOI MOSFETs Solid State Device Research Conference, 1990. ESSDERC'90. 20th European , pp.445-448 [Details]
(1997)8th International Symposium on SOI technology and devices (ECS 1997)
Chen, J and Colinge, Jean-Pierre and Flandre, Denis and Gillon, R and Raskin, Jean-Pierre and Vanhoenacker-Janvier, Danielle and others (1997) Investigation of SALICIDE processes for thin-film SOI microwave applications 8th International Symposium on SOI technology and devices (ECS 1997) [Details]
(1993)Radiation and its Effects on Components and Systems, 1993., RADECS 93., Second European Conference on
Simoen, E and Magnusson, U and Van den Bosch, G and Smeys, P and Colinge, JP and Claeys, C (1993) Low-frequency noise and DC characterization of ionization damage in a 1-$\mu$m SOI CMOS technology adapted for space applications Radiation and its Effects on Components and Systems, 1993., RADECS 93., Second European Conference on , pp.365-372 [Details]
(2010)2010 EUROSOI Conference
Yan, Ran and Cullen, Ailbhe and Afzalian, Aryan and Ferain, Isabelle and Lee, Chi-Woo and Dehdashti, Nima and Razavi, Pedram and Colinge, Jean-Pierre and others (2010) 3D Simulation of RTS Amplitude in Accumulation-Mode and Inversion-Mode Trigate SOI MOSFETs 2010 EUROSOI Conference [Details]
(2001)MAR01 Meeting of the American Physical Society 2001
Bayot, Vincent and Tang, Xiaohui and Baie, Xavier and Colinge, Jean-Pierre and Van de Wiele, Fernand and others (2001) SOI Self-Aligned Single-Electron Memory MAR01 Meeting of the American Physical Society 2001 [Details]
(1997)1997 International Symposium on VLSI Technology, Systems, and Applications Proceedings of Technical Papers
Colinge, Jean-Pierre and others (1997) Status and trends in SOI CMOS technology 1997 International Symposium on VLSI Technology, Systems, and Applications Proceedings of Technical Papers [Details]
(2001)Silicon-On-Insulator Technology and Devices X. Proceedings of the Tenth International Symposium
Tang, Xiaohui and Baie, X and Colinge, JP and Van De Wiele, F and Bayot, Vincent and others (2001) Effect of quantum confinement in SOI single-hole transistors Silicon-On-Insulator Technology and Devices X. Proceedings of the Tenth International Symposium [Details]
(2001)MAR01 Meeting of the American Physical Society 2001
Bayot, Vincent and Tang, Xiaohui and Baie, Xavier and Colinge, Jean-Pierre and others (2001) Quantum Confinement Based SOI Single-hole Transistor MAR01 Meeting of the American Physical Society 2001 [Details]
(1995)25th Solid State Device Research Conference (ESSDERC 1995)
Francis, P and Flandre, Denis and Colinge, Jean-Pierre and Van de Wiele, Fernand and others (1995) Comparison of self-heating in effects in GAA and SOI devices 25th Solid State Device Research Conference (ESSDERC 1995) [Details]
(1998)Microwave Eng. Workshop on New technologies for RF devices
Gillon, Renaud and Colinge, Jean-Pierre and Flandre, Denis and Raskin, Jean-Pierre and Vanhoenacker-Janvier, Danielle and others (1998) Silicon-on-insulator for RF and microwave applications Microwave Eng. Workshop on New technologies for RF devices [Details]
(1997)Conference HITEN 1997
Chen, J and Colinge, Jean-Pierre and Flandre, Denis and Nguyen, B-Y and Hegde, R and Rai, R and others (1997) Formation of TiN/CoSi2 barrier layer on thin-film SOI for high-temperature applications Conference HITEN 1997 [Details]
(1991)SOI Conference, 1991. Proceedings, 1991., IEEE International
Simoen, E and Gao, MH and Colinge, JP and Claeys, C (1991) Study of hot-carrier stress effects on the DC characteristics of SOI NMOST's operating at 4.2 K SOI Conference, 1991. Proceedings, 1991., IEEE International , pp.2-3 [Details]
(1989)SOS/SOI Technology Conference, 1989., 1989 IEEE
Tokunaga, K and Sturm, JC and Colinge, JP (1989) Substrate bias and temperature dependence of anomalous subthreshold slopes in fully-depleted submicron SOI MOSFETs SOS/SOI Technology Conference, 1989., 1989 IEEE , pp.15-16 [Details]
(2007)IEEK 2007 Summer Conference
Lee, Chi-Woo and Lederer, Dimitri and Afzalian, Aryan and Yan, Ran and Colinge, Jean-Pierre and others (2007) Simulation of fluorine implant effects in metal-gate FD-SOI and MuGFET IEEK 2007 Summer Conference [Details]
(1997)Conf\'erence Faible Tension Faible Consommation (FTFC 1997)
Jespers, Paul and Colinge, Jean-Pierre and Flandre, Denis and others (1997) Low-voltage low-power potential of SOI (Silicon on Insulator) Conf\'erence Faible Tension Faible Consommation (FTFC 1997) [Details]
(1990)Brazil-DL tentative
Martino, Joad A and Lauwers, L and Colinge, Jean P (1990) Analytical model for the potential drop in the silicon substrate on thin-film SOI MOSFETs and its influence on the threshold voltage Brazil-DL tentative , pp.64-73 [Details]
(1994)IX Brazilian Microelectronics Society Congress
Flandre, Denis and Colinge, Jean-Pierre and others (1994) High-temperature SOI technology IX Brazilian Microelectronics Society Congress [Details]
(2001)2001 Electrochemical Society Conference
Vandooren, Anne and Cristoloveanu, Sorin and Colinge, Jean-Pierre and Flandre, Denis and others (2001) Performance of double-gate SOI NMOSFETs at low temperature 2001 Electrochemical Society Conference [Details]
(1997)International Conference on Solid-State Devices and Materials (SSDM 1997)
Tang, Xiaohui and Baie, Xavier and Colinge, Jean-Pierre and others (1997) Fabrication process of Si memory dot and quantum channel based on as dopant statistical distribution effect International Conference on Solid-State Devices and Materials (SSDM 1997) [Details]
(2008)IEEE International SOI conference: SOI Fundamentals Class
Colinge, Jean-Pierre and Flandre, Denis and others (2008) SOI Devices IEEE International SOI conference: SOI Fundamentals Class [Details]
(2010)2010 EUROSOI Conference
Lee, Chi-Woo and Borne, A and Ferain, Isabelle and Afzalian, Aryan and Yan, Ran and Dehdashti-Akhavan, Nima and Razavi, P and Colinge, Jean-Pierre and others (2010) Substrate bias effects in MuGFETs 2010 EUROSOI Conference [Details]
(2008)4th EuroSOI Workshop 2008
Colinge, Jean-Pierre and Afzalian, Aryan and Lederer, Dimitri and Lee, Chi-Woo and Yan, Ran and others (2008) Influence of Carrier Confinement on the Subthreshold Swing of Multigate SOI MOSFETs 4th EuroSOI Workshop 2008 [Details]
(2011)Ultimate Integration on Silicon (ULIS), 2011 12th International Conference on
Nazarov, AN and Lee, C-W and Kranti, A and Ferain, I and Yan, R and Dehdashti Akhavan, N and Razavi, P and Yu, R and Colinge, JP (2011) Extraction of channel mobility in nanowire MOSFETs using I d (Vg) characteristics and random telegraph noise amplitude Ultimate Integration on Silicon (ULIS), 2011 12th International Conference on , pp.1-3 [Details]
(1982)VLSI Technology, 1982. Digest of Technical Papers. Symposium on
Colinge, JP and Demoulin, E and Bensahel, D and Auvert, C (1982) The Selective Annealing Technique: An-Overview VLSI Technology, 1982. Digest of Technical Papers. Symposium on , pp.84-85 [Details]
(2013)VLSI Technology, Systems, and Applications (VLSI-TSA), 2013 International Symposium on
Colinge, J-P (2013) 3D transistors VLSI Technology, Systems, and Applications (VLSI-TSA), 2013 International Symposium on , pp.1-2 [Details]
(1988)SOS/SOI Technology Workshop, 1988. Proceedings., 1988 IEEE
Colinge, JP and Kang, J and McFarland, W and Stout, C and Walker, R (1988) Gigahertz CMOS/SIMOX circuits SOS/SOI Technology Workshop, 1988. Proceedings., 1988 IEEE [Details]
(2000)ESSDERC 2000. Proceedings of the 30th European Solid-State Device Research Conference
Tang, Xiaohui and Baie, Xavier and Colinge, Jean-Pierre and Van de Wiele, Fernand and Bayot, Vincent and others (2000) Quantum effects in SOI single-hole transistors ESSDERC 2000. Proceedings of the 30th European Solid-State Device Research Conference [Details]
(2008)Invited paper, panel session, 4th EUROSOI Workshop, Cork, Ireland
Cristoloveanu, S and Colinge, J-P and Faynot, O and Claeys, C and Okhonin, S and Bretegnier, D and others (2008) What are the critical issues for SOI? Invited paper, panel session, 4th EUROSOI Workshop, Cork, Ireland [Details]
(1988)SOS/SOI Technology Workshop, 1988. Proceedings., 1988 IEEE
Ioannou, DE and Mclarty, PK and Hughes, HL and Colinge, JP (1988) Deep traps in very thin SIMOX MOSFET by current DLTS SOS/SOI Technology Workshop, 1988. Proceedings., 1988 IEEE [Details]
(1997)27th European Microwave Conference, EuMC'97
Huynen, Isabelle and Raskin, Jean-Pierre and Vanhoenacker-Janvier, Danielle and Colinge, Jean-Pierre and others (1997) Modeling and measurements of inductive elements on SIMOX substrates 27th European Microwave Conference, EuMC'97 [Details]
(1999)1999 NASA/JPL conference on Electronics for Extreme Environments
Flandre, Denis and Dessard, Vincent and Deme\^us, Laurent and Viviani, A and Colinge, Jean-Pierre and others (1999) Fully-depleted SOI CMOS circuits for operation above 250° C 1999 NASA/JPL conference on Electronics for Extreme Environments [Details]
(2010)2010 EUROSOI Conference
Dehdashti, Nima and Afzalian, Aryan and Lee, Chi-Woo and Yan, Ran and Ferain, Isabelle and Razavi, Pedram and Colinge, Jean-Pierre and others (2010) Effect of intravalley acoustic phonon scattering on mobility in silicon nanowire transistor 2010 EUROSOI Conference [Details]
(1999)SOI Conference, 1999. Proceedings. 1999 IEEE International
Tang, Xiaohui and Baie, Xavier and Bayot, Vincent and Van de Wiele, Fernand and Colinge, Jean-Pierre (1999) An SOI nano flash memory device SOI Conference, 1999. Proceedings. 1999 IEEE International , pp.100-101 [Details]
(1998)Microwave Conference, 1998. 28th European
Dambrine, G and Raskin, Jean-Pierre and Danneville, F and Vanhoenacker, D and Colinge, Jean-Pierre and Picheta, L and Cappy, A (1998) Silicon-On-Insulator-Based Technology MOSFET: Prospects For Application to Low Noise RF Integrated Circuits Microwave Conference, 1998. 28th European , pp.721-726 [Details]
(2014)Simulation of Semiconductor Processes and Devices (SISPAD), 2014 International Conference on
Colinge, J-P (2014) Multigate transistors: Pushing Moore's law to the limit Simulation of Semiconductor Processes and Devices (SISPAD), 2014 International Conference on , pp.313-316 [Details]
(2001)199th Meeting of the Electrochemical Society 2001
Tang, Xiaohui and Baie, Xavier and Colinge, Jean-Pierre and Van de Wiele, Fernand and Bayot, Vincent and others (2001) New Quantum-Confinement Based SOI Single-Hole Transistor 199th Meeting of the Electrochemical Society 2001 [Details]
(2001)Silicon-On-Insulator Technology and Devices X. Proceedings of the Tenth International Symposium
Tang, Xiaohui and Baie, X and Colinge, JP and Van De Wiele, F and Bayot, Vincent and others (2001) Self-consistent simulation of nano scale SOI devices: the case of nano flash memory Silicon-On-Insulator Technology and Devices X. Proceedings of the Tenth International Symposium [Details]
(1998)Solid-State Device Research Conference, 1998. Proceeding of the 28th European
Ernst, Thomas and Cristoloveanu, Sorin and Vandooren, Anne and Colinge, Jean-Pierre and Flandre, Denis (1998) Recombination Current and Carrier Lifetime Extraction in Dual-Gate Fully Depleted SOI Devices Solid-State Device Research Conference, 1998. Proceeding of the 28th European , pp.272-275 [Details]
(2001)199th Meeting of the Electrochemical Society 2001
Tang, Xiaohui and Baie, Xavier and Colinge, Jean-Pierre and Van de Wiele, Fernand and Bayot, Vincent and others (2001) Fabrication of a Self-Aligned SOI Nano Flash Memory Device 199th Meeting of the Electrochemical Society 2001 [Details]
(1994)Second International High temperature Conference
Flandre, Denis and Gentinne, B and Eggermont, Jean-Paul and De Ceuster, D and Colinge, Jean-Pierre and Jespers, Paul and others (1994) CMOS on SOI operational amplifiers for application up to 300° C Second International High temperature Conference [Details]
(2009)5th EuroSOI Workshop 2009
Dehdashti, Nima and Afzalian, Aryan and Lee, Chi-Woo and Yan, Ran and Fagas, Giorgos and Colinge, Jean-Pierre and others (2009) Transport in Triple-Gate Si Nanowires using a full-3D Real-Space NEGF Simulator 5th EuroSOI Workshop 2009 [Details]
(2009)13th International Workshop on Computational Electronics (IWCE 2009)
Dehdashti Akhavan, Nima and Afzalian, Aryan and Lee, Chi-Woo and Yan, Ran and Fagas, Giorgos and Colinge, Jean-Pierre and others (2009) Device characteristics of Trigate-FET with barrier constrictions in the channel 13th International Workshop on Computational Electronics (IWCE 2009) [Details]
(1995)NUTEK CONSORTIA Workshop on Si-Processing and High Frequency Devices
Gillon, Renaud and Raskin, Jean-Pierre and Colinge, Jean-Pierre and Chen, Jian and Vanhoenacker-Janvier, Danielle and others (1995) Low Power/High Frequency devices on SOI NUTEK CONSORTIA Workshop on Si-Processing and High Frequency Devices [Details]
(1993)IEEE International SOI Conference, 1993
Flandre, Denis and Francis, P and Colinge, Jean-Pierre and Cristoloveanu, Sorin and others (1993) Comparison of hot-carrier effects in thin-film accumulation-mode SOI and GAA p-MOSFETs IEEE International SOI Conference, 1993 [Details]
(2008)Proceeding 4th EuroSOI Workshop
Aryan Afzalian, Dimitri Lederer, Chi-Woo Lee, Ran Yan and Jean-Pierre Colinge Proceeding 4th EuroSOI Workshop (2008) Ultra Scaled MultiGate SOI MOSFETs: Accumulation-Mode vs. Inversion-Mode Proceeding 4th EuroSOI Workshop [Details]
(2008)Proceeding 4th EuroSOI Workshop
Ran Yan, Aryan Afzalian, Dimitri Lederer, Chi-Woo Lee, and Jean-Pierre Colinge, (2008) Doping Fluctuation Effects in Trigate SOI MOSFETs” Proceeding 4th EuroSOI Workshop [Details]
(1995)International Electron Devices Meeting 1995 (IEDM 1995)
Raskin, Jean-Pierre and Viviani, A and Flandre, Denis and Colinge, Jean-Pierre and Vanhoenacker-Janvier, Danielle and others (1995) Extended study of crosstalk in SOI-SIMOX substrates International Electron Devices Meeting 1995 (IEDM 1995) [Details]
(2004)Solid-State Device Research conference, 2004. ESSDERC 2004. Proceeding of the 34th European
Colinge, J (2004) Novel gate concepts for MOS devices Solid-State Device Research conference, 2004. ESSDERC 2004. Proceeding of the 34th European , pp.45-49 [Details]
(1992)Electron Devices Meeting, 1992. IEDM'92. Technical Digest., International
Francis, P and Terao, Akira and Gentinne, Bernard and Flandre, Denis and Colinge, J-P (1992) SOI technology for high-temperature applications Electron Devices Meeting, 1992. IEDM'92. Technical Digest., International , pp.353-356 [Details]
(2009)SOI Conference, 2009 IEEE International
Colinge, Jean-Pierre and Lee, C-W and Afzalian, Aryan and Dehdashti, Nima and Yan, Ran and Ferain, Isabelle and Razavi, P and O'Neill, B and Blake, A and White, M and others (2009) SOI gated resistor: CMOS without junctions SOI Conference, 2009 IEEE International , pp.1-2 [Details]
(1995)SOI Conference, 1995. Proceedings., 1995 IEEE International
Baie, X and Colinge, JP and Bayot, V and Grivei, E (1995) Quantum-wire effects in thin and narrow SOI MOSFETs SOI Conference, 1995. Proceedings., 1995 IEEE International , pp.66-67 [Details]
(1990)SOS/SOI Technology Conference, 1990., 1990 IEEE
Colinge, J-P and Gao, MH and Romano, A and Maes, H and Claeys, C (1990) Silicon-on-insulatorgate-all-around'MOS device SOS/SOI Technology Conference, 1990., 1990 IEEE , pp.137-138 [Details]
(1989)Electron Devices Meeting, 1989. IEDM'89. Technical Digest., International
Colinge, J-P (1989) Thin-film SOI technology: the solution to many submicron CMOS problems Electron Devices Meeting, 1989. IEDM'89. Technical Digest., International , pp.817-820 [Details]
(1994)Electron Devices Meeting, 1994. IEDM'94. Technical Digest., International
Colinge, J-P (1994) Recent advances in SOI technology Electron Devices Meeting, 1994. IEDM'94. Technical Digest., International , pp.817-820 [Details]
(1996)SOI Conference, 1996. Proceedings., 1996 IEEE International
Colinge, Jean-Pierre and Chen, J and Flandre, Denis and Raskin, Jean-Pierre and Gillon, R and Vanhoenacker, D (1996) A low-voltage, low-power microwave SOI MOSFET SOI Conference, 1996. Proceedings., 1996 IEEE International , pp.128-129 [Details]
(2002)IEEE International SOI conference
Xiong, W and Ramkumar, K and Jang, SJ and PARKS, J-T and Colinge, J-P (2002) Self-aligned ground-plane FDSOI MOSFET IEEE International SOI conference , pp.23-24 [Details]
(2002)Microelectronics, 2002. MIEL 2002. 23rd International Conference on
Colinge, JP and Park, JT and Colinge, CA (2002) SOI devices for sub-0.1 $\mu$m gate lengths Microelectronics, 2002. MIEL 2002. 23rd International Conference on , pp.109-113 [Details]
(1992)SOI Conference, 1992. IEEE International
Verhaege, K and Groeseneken, G and Colinge, JP and Maes, HE (1992) Analysis of snapback in SOI nMOSFETs and its use for an SOI ESD protection circuit SOI Conference, 1992. IEEE International , pp.140-141 [Details]
(2006)Solid-State Device Research Conference, 2006. ESSDERC 2006. Proceeding of the 36th European
Molzer, W and Schulz, Th and Xiong, W and Cleavelin, RC and Schrufer, K and Marshall, A and Matthews, K and Sedlmeir, J and Siprak, D and Knoblinger, G and others (2006) Self heating simulation of multi-gate FETs Solid-State Device Research Conference, 2006. ESSDERC 2006. Proceeding of the 36th European , pp.311-314 [Details]
(1995)Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International
Colinge, Jean-Pierre and Eggermont, Jean-Paul and Flandre, Denis and Francis, Pascale and Jespers, PGA (1995) Potential of SOI for analog and mixed analog-digital low-power applications Solid-State Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International , pp.194-195 [Details]
(1981)Electron Devices Meeting, 1981 International
Colinge, JP and Demoulin, E (1981) ST-CMOS (stacked transistors CMOS): a double-poly-NMOS-compatible CMOS technology Electron Devices Meeting, 1981 International , pp.557-560 [Details]
(2007)Semiconductor Conference, 2007. CAS 2007. International
Colinge, J (2007) From gate-all-around to nanowire MOSFETs Semiconductor Conference, 2007. CAS 2007. International , pp.11-17 [Details]
(2001)SOI Conference, 2001 IEEE International
Park, JT and Colinge, CA and Colinge, JP (2001) Comparison of gate structures for short-channel SOI MOSFETs SOI Conference, 2001 IEEE International , pp.115-116 [Details]
(2005)SOI Conference, 2005. Proceedings. 2005 IEEE International
Schulz, T and Xiong, W and Cleavelin, CR and Schruefer, K and Gostkowski, M and Matthews, K and Gebara, G and Zaman, RJ and Patruno, P and Chaudhry, A and others (2005) Fin thickness asymmetry effects in multiple-gate SOI FETs (MuGFETs) SOI Conference, 2005. Proceedings. 2005 IEEE International , pp.154-156 [Details]

Professional Activities

Honours and Awards

 YearTitleAwarding Body
2012IEEE Andrew Grove Award IEEE
2011• Medal of the Institute of Semiconductor Physics Ukrainian academy of Sciences
2005Walton Fellowship Science Foundation Ireland
2010Researcher of the Year Science Foundation Ireland
1992Biennal Siemens Award Siemens
2010Inventor of the Year University College Cork

Employment

 EmployerPositionFrom / To
TSMC Director TCAD Division01-APR-12 / 16-SEP-14
Tyndall National Institute Head of the Micro-Nanoelectronics Centre01-JAN-08 /
Centre National d'Etudes des Télécommunications (CNET), Researcher01-JAN-81 /
Université Catholique de Louvain Professor Faculty of Applied Sciences, Department of Electricity (ELEC), Microelectronics Laboratory (DICE)01-JAN-91 /
University of California Professor01-JAN-97 /
Tyndall National Institute Senior Staff Researcher01-JAN-06 /
Hewlett-Packard Research Labs Technical Staff01-JAN-85 /
IMEC Project Leader01-JAN-88 /

Education

 YearInstitutionQualificationSubject
1984Université Catholique de Louvain PhDApplied Sciences
1980Université Catholique de Louvain DiplomaElectrical Engineering
1980Université Catholique de Louvain DiplomaPhilosophy

Contact details

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School of Biological, Earth and Environmental Sciences

An Scoil Eolaíochtaí Bitheolaíocha, Domhaneolaíocha agus Comhshaoil

University College Cork, Distillery Fields, North Mall, Cork, Ireland T23 N73K

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