TY  - JOUR
  - Mincica, M,Pepe, D,Zito, D
  - 2011
  - January
  - IEEE Transactions On Circuits and Systems I-Regular Papers
  - CMOS UWB Multiplier
  - Validated
  - ()
  - CMOS multiplier radar radio-frequency (RF) integrated circuit ultrawideband (UWB) LOW-POWER LNA
  - 58
  - 570
  - 574
  - A fully differential analog multiplier for wideband operations is presented. The circuit consists of a p-MOSFET common-gate differential pair input stage for wideband impedance matching, a p-MOSFET Gilbert quad as a multiplier stage, and active loads. The circuit has been designed and fabricated in 90-nm CMOS. The test-chip area is 560 x 700 mu m(2). The overall power consumption is 3.7 mW from a 1.2-V power supply. In the case of input monocycle pulses with duration time of 700 ps, the measurements show an input-output energy ratio equal to 2, a conversion gain of 12.7 dB at intermediate frequencies in the range of 0.001-10 MHz for input tones in the range of 2-4 GHz, a noise figure of 14.4 dB (minimum) and compression points of -3.5 and -2 dBm for the two inputs. The performance of the proposed multiplier favorably compares with the state of the art.
  - DOI 10.1109/TCSII.2011.2161175
DA  - 2011/01
ER  - 

@article{V108834277,
   = {Mincica,  M and Pepe,  D and Zito,  D },
   = {2011},
   = {January},
   = {IEEE Transactions On Circuits and Systems I-Regular Papers},
   = {CMOS UWB Multiplier},
   = {Validated},
   = {()},
   = {CMOS multiplier radar radio-frequency (RF) integrated circuit ultrawideband (UWB) LOW-POWER LNA},
   = {58},
  pages = {570--574},
   = {{A fully differential analog multiplier for wideband operations is presented. The circuit consists of a p-MOSFET common-gate differential pair input stage for wideband impedance matching, a p-MOSFET Gilbert quad as a multiplier stage, and active loads. The circuit has been designed and fabricated in 90-nm CMOS. The test-chip area is 560 x 700 mu m(2). The overall power consumption is 3.7 mW from a 1.2-V power supply. In the case of input monocycle pulses with duration time of 700 ps, the measurements show an input-output energy ratio equal to 2, a conversion gain of 12.7 dB at intermediate frequencies in the range of 0.001-10 MHz for input tones in the range of 2-4 GHz, a noise figure of 14.4 dB (minimum) and compression points of -3.5 and -2 dBm for the two inputs. The performance of the proposed multiplier favorably compares with the state of the art.}},
   = {DOI 10.1109/TCSII.2011.2161175},
  source = {IRIS}
}