TY  - JOUR
  - Kerins T., Marnane W. P., Popovici E. M., Baretto P.S.L.M
  - 2005
  - October
  - IEE Proceedings - Information Security
  - Hardware Accelerators for Pairing based Cryptosystems
  - Published
  - ()
  - 152
  - 1
  - 47
  - 56
  - Polynomial basis hardware architectures are described for the mathematical operations required in pairing based cryptosystems in characteristic p=3. In hardware, arithmetic operations in extension fields of GF(3^m) can be parallelised, and this results in high performance dedicated processors for efficient Tate pairing calculation. The implementationaspects of two such hardware processors are discussed through prototyping over GF(3^97) on the Xilinx Virtex2 and Virtex2Pro FPGA technologies.
  - 1747-0722
  - 10.1049/ip-ifs: 20055009
  - Enterprise Ireland
DA  - 2005/10
ER  - 

@article{V349645,
   = {Kerins T.,  Marnane W. P. and  Popovici E. M.,  Baretto P.S.L.M },
   = {2005},
   = {October},
   = {IEE Proceedings - Information Security},
   = {Hardware Accelerators for Pairing based Cryptosystems},
   = {Published},
   = {()},
   = {152},
   = {1},
  pages = {47--56},
   = {{Polynomial basis hardware architectures are described for the mathematical operations required in pairing based cryptosystems in characteristic p=3. In hardware, arithmetic operations in extension fields of GF(3^m) can be parallelised, and this results in high performance dedicated processors for efficient Tate pairing calculation. The implementationaspects of two such hardware processors are discussed through prototyping over GF(3^97) on the Xilinx Virtex2 and Virtex2Pro FPGA technologies.}},
  issn = {1747-0722},
   = {10.1049/ip-ifs: 20055009},
   = {Enterprise Ireland},
  source = {IRIS}
}