Reduced complexity, FPGA implementation of quasi-cyclic LDPC decoder

Typeset version

 

TY  - CONF
  - Spagnol, C.; Marnane, W.; Popovici, E.;
  - European Conference on Circuit Theory and Design, 2005
  - Reduced complexity, FPGA implementation of quasi-cyclic LDPC decoder
  - 2005
  - August
  - Published
  - 1
  - ()
  - IEEE
  - 613
  - 618
  - 29-AUG-05
  - 01-SEP-05
DA  - 2005/08
ER  - 
@inproceedings{V377585,
   = {Spagnol, C. and  Marnane, W. and  Popovici, E. and },
   = {European Conference on Circuit Theory and Design, 2005},
   = {{Reduced complexity, FPGA implementation of quasi-cyclic LDPC decoder}},
   = {2005},
   = {August},
   = {Published},
   = {1},
   = {()},
   = {IEEE },
  pages = {613--618},
  month = {Aug},
   = {01-SEP-05},
  source = {IRIS}
}
AUTHORSSpagnol, C.; Marnane, W.; Popovici, E.;
TITLEEuropean Conference on Circuit Theory and Design, 2005
PUBLICATION_NAMEReduced complexity, FPGA implementation of quasi-cyclic LDPC decoder
YEAR2005
MONTHAugust
STATUSPublished
PEER_REVIEW1
TIMES_CITED()
SEARCH_KEYWORD
EDITORSIEEE
START_PAGE613
END_PAGE618
LOCATION*
START_DATE29-AUG-05
END_DATE01-SEP-05
ABSTRACT
FUNDED_BY*
URL
DOI_LINK
FUNDING_BODY
GRANT_DETAILS