15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process

J. Mitard; L. Witters; R. Loo; S. H. Lee; J. W. Sun; J. Franco; L. Ragnarsson; A. Brand; X. Lu; N. Yoshida; G. Eneman; D. P. Brunco; M. Vorderwestner; P. Storck; A. P. Milenin; A. Hikavyy; N. Waldron; P. Favia; D. Vanhaeren; A. Vanderheyden; R. Olivier; H. Mertens; H. Arimura; S. Sonja; C. Vrancken; H. Bender; P. Eyben; K. Barla; S. G. Lee; N. Horiguchi; N. Collaert; A. V.Y. Thean

doi:10.1109/VLSIT.2014.6894391

15nm-W_FIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process

J. Mitard
, L. Witters
, R. Loo
, S. H. Lee
, J. W. Sun
, J. Franco
, L. Ragnarsson
, A. Brand
, X. Lu
, N. Yoshida
, G. Eneman
, D. P. Brunco
, M. Vorderwestner
, P. Storck
, A. P. Milenin
, A. Hikavyy
, N. Waldron
, P. Favia
, D. Vanhaeren
, A. Vanderheyden

R. Olivier, H. Mertens, H. Arimura, S. Sonja, C. Vrancken, H. Bender, P. Eyben, K. Barla, S. G. Lee, N. Horiguchi, N. Collaert, A. V.Y. Thean

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

Abstract

An STI-last integration scheme was successfully developed to fabricate low-defectivity and dopant-controlled SiGe SRB / sGe Fins. For the first time, 15 nm fin-width SiGe SRB/highly-strained Ge pFinFETs are demonstrated down to 35 nm gate length. With a CET_INV-normalized G_M,SAT,INT of 6.7 nm.mS/μm, the Si_0.3Ge_0.7 / sGe pFinFETs presented in this work improve the performance by 90% as compared to the state-of-the-art relaxed-Ge FinFETs.

Original language	English
Title of host publication	Digest of Technical Papers - Symposium on VLSI Technology
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479933310
DOIs	https://doi.org/10.1109/VLSIT.2014.6894391
Publication status	Published - 8 Sep 2014
Externally published	Yes
Event	34th Symposium on VLSI Technology, VLSIT 2014 - Honolulu, United States Duration: 9 Jun 2014 → 12 Jun 2014

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)	0743-1562

Conference

Conference	34th Symposium on VLSI Technology, VLSIT 2014
Country/Territory	United States
City	Honolulu
Period	9/06/14 → 12/06/14

Access to Document

10.1109/VLSIT.2014.6894391

Cite this

Mitard, J., Witters, L., Loo, R., Lee, S. H., Sun, J. W., Franco, J., Ragnarsson, L., Brand, A., Lu, X., Yoshida, N., Eneman, G., Brunco, D. P., Vorderwestner, M., Storck, P., Milenin, A. P., Hikavyy, A., Waldron, N., Favia, P., Vanhaeren, D., ... Thean, A. V. Y. (2014). 15nm-W_FIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process. In Digest of Technical Papers - Symposium on VLSI Technology Article 6894391 (Digest of Technical Papers - Symposium on VLSI Technology). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.2014.6894391

@inproceedings{6d4ceefec4e04a0daa141f63f9f1bab7,

title = "15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process",

abstract = "An STI-last integration scheme was successfully developed to fabricate low-defectivity and dopant-controlled SiGe SRB / sGe Fins. For the first time, 15 nm fin-width SiGe SRB/highly-strained Ge pFinFETs are demonstrated down to 35 nm gate length. With a CETINV-normalized GM,SAT,INT of 6.7 nm.mS/μm, the Si0.3Ge0.7 / sGe pFinFETs presented in this work improve the performance by 90\% as compared to the state-of-the-art relaxed-Ge FinFETs.",

author = "J. Mitard and L. Witters and R. Loo and Lee, \{S. H.\} and Sun, \{J. W.\} and J. Franco and L. Ragnarsson and A. Brand and X. Lu and N. Yoshida and G. Eneman and Brunco, \{D. P.\} and M. Vorderwestner and P. Storck and Milenin, \{A. P.\} and A. Hikavyy and N. Waldron and P. Favia and D. Vanhaeren and A. Vanderheyden and R. Olivier and H. Mertens and H. Arimura and S. Sonja and C. Vrancken and H. Bender and P. Eyben and K. Barla and Lee, \{S. G.\} and N. Horiguchi and N. Collaert and Thean, \{A. V.Y.\}",

note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 34th Symposium on VLSI Technology, VLSIT 2014 ; Conference date: 09-06-2014 Through 12-06-2014",

year = "2014",

month = sep,

day = "8",

doi = "10.1109/VLSIT.2014.6894391",

language = "English",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "Digest of Technical Papers - Symposium on VLSI Technology",

address = "United States",

}

Mitard, J, Witters, L, Loo, R, Lee, SH, Sun, JW, Franco, J, Ragnarsson, L, Brand, A, Lu, X, Yoshida, N, Eneman, G, Brunco, DP, Vorderwestner, M, Storck, P, Milenin, AP, Hikavyy, A, Waldron, N, Favia, P, Vanhaeren, D, Vanderheyden, A, Olivier, R, Mertens, H, Arimura, H, Sonja, S, Vrancken, C, Bender, H, Eyben, P, Barla, K, Lee, SG, Horiguchi, N, Collaert, N & Thean, AVY 2014, 15nm-W_FIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process. in Digest of Technical Papers - Symposium on VLSI Technology., 6894391, Digest of Technical Papers - Symposium on VLSI Technology, Institute of Electrical and Electronics Engineers Inc., 34th Symposium on VLSI Technology, VLSIT 2014, Honolulu, United States, 9/06/14. https://doi.org/10.1109/VLSIT.2014.6894391

15nm-W_FIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process. / Mitard, J.; Witters, L.; Loo, R. et al.
Digest of Technical Papers - Symposium on VLSI Technology. Institute of Electrical and Electronics Engineers Inc., 2014. 6894391 (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

TY - GEN

T1 - 15nm-WFIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process

AU - Mitard, J.

AU - Witters, L.

AU - Loo, R.

AU - Lee, S. H.

AU - Sun, J. W.

AU - Franco, J.

AU - Ragnarsson, L.

AU - Brand, A.

AU - Lu, X.

AU - Yoshida, N.

AU - Eneman, G.

AU - Brunco, D. P.

AU - Vorderwestner, M.

AU - Storck, P.

AU - Milenin, A. P.

AU - Hikavyy, A.

AU - Waldron, N.

AU - Favia, P.

AU - Vanhaeren, D.

AU - Vanderheyden, A.

AU - Olivier, R.

AU - Mertens, H.

AU - Arimura, H.

AU - Sonja, S.

AU - Vrancken, C.

AU - Bender, H.

AU - Eyben, P.

AU - Barla, K.

AU - Lee, S. G.

AU - Horiguchi, N.

AU - Collaert, N.

AU - Thean, A. V.Y.

PY - 2014/9/8

Y1 - 2014/9/8

N2 - An STI-last integration scheme was successfully developed to fabricate low-defectivity and dopant-controlled SiGe SRB / sGe Fins. For the first time, 15 nm fin-width SiGe SRB/highly-strained Ge pFinFETs are demonstrated down to 35 nm gate length. With a CETINV-normalized GM,SAT,INT of 6.7 nm.mS/μm, the Si0.3Ge0.7 / sGe pFinFETs presented in this work improve the performance by 90% as compared to the state-of-the-art relaxed-Ge FinFETs.

AB - An STI-last integration scheme was successfully developed to fabricate low-defectivity and dopant-controlled SiGe SRB / sGe Fins. For the first time, 15 nm fin-width SiGe SRB/highly-strained Ge pFinFETs are demonstrated down to 35 nm gate length. With a CETINV-normalized GM,SAT,INT of 6.7 nm.mS/μm, the Si0.3Ge0.7 / sGe pFinFETs presented in this work improve the performance by 90% as compared to the state-of-the-art relaxed-Ge FinFETs.

UR - https://www.scopus.com/pages/publications/84907701807

U2 - 10.1109/VLSIT.2014.6894391

DO - 10.1109/VLSIT.2014.6894391

M3 - Conference proceeding

AN - SCOPUS:84907701807

T3 - Digest of Technical Papers - Symposium on VLSI Technology

BT - Digest of Technical Papers - Symposium on VLSI Technology

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 34th Symposium on VLSI Technology, VLSIT 2014

Y2 - 9 June 2014 through 12 June 2014

ER -

Mitard J, Witters L, Loo R, Lee SH, Sun JW, Franco J et al. 15nm-W_FIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process. In Digest of Technical Papers - Symposium on VLSI Technology. Institute of Electrical and Electronics Engineers Inc. 2014. 6894391. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSIT.2014.6894391