3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability

A. Vandooren; J. Franco; B. Parvais; Z. Wu; L. Witters; A. Walke; W. Li; L. Peng; V. Desphande; F. M. Bufler; N. Rassoul; G. Hellings; G. Jamieson; F. Inoue; G. Verbinnen; K. Devriendt; L. Teugels; N. Heylen; E. Vecchio; T. Zheng; E. Rosseel; W. Vanherle; A. Hikavyy; B. T. Chan; R. Ritzenthaler; G. Besnard; W. Schwarzenbach; G. Gaudin; I. Radu; B. Y. Nguyen; N. Waldron; V. De Heyn; D. Mocuta; N. Collaert

doi:10.1109/VLSIT.2018.8510705

3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability

A. Vandooren
, J. Franco
, B. Parvais
, Z. Wu
, L. Witters
, A. Walke
, W. Li
, L. Peng
, V. Desphande
, F. M. Bufler
, N. Rassoul
, G. Hellings
, G. Jamieson
, F. Inoue
, G. Verbinnen
, K. Devriendt
, L. Teugels
, N. Heylen
, E. Vecchio
, T. Zheng

E. Rosseel, W. Vanherle, A. Hikavyy, B. T. Chan, R. Ritzenthaler, G. Besnard, W. Schwarzenbach, G. Gaudin, I. Radu, B. Y. Nguyen, N. Waldron, V. De Heyn, D. Mocuta, N. Collaert

Interuniversitair Micro-Elektronica Centrum
Vrije Universiteit Brussel
Swiss Federal Institute of Technology Zurich
Soitec S.A.

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

Abstract

3D sequential integration requires top MOSFETs processed at low thermal budget, which can impair the device reliability. In this work, top junction-less device are fabricated with a maximum processing temperature of 525°C. The devices feature high k /metal replacement gate and low temperature Si:P and SiGe:B 60% raised SD for NMOS and PMOS respectively. Device matching, analog and RF performance of the top tier devices are in-line with state-of-the-art Si technology processed at high temperature (>1000°C). The top Si layer is transferred on CMOS planar bulk wafers with W metal-1 interconnects, using a SiCN to SiCN direct wafer bonding.

Original language	English
Title of host publication	2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	69-70
Number of pages	2
ISBN (Electronic)	9781538642160
DOIs	https://doi.org/10.1109/VLSIT.2018.8510705
Publication status	Published - 25 Oct 2018
Externally published	Yes
Event	38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 - Honolulu, United States Duration: 18 Jun 2018 → 22 Jun 2018

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2018-June
ISSN (Print)	0743-1562

Conference

Conference	38th IEEE Symposium on VLSI Technology, VLSI Technology 2018
Country/Territory	United States
City	Honolulu
Period	18/06/18 → 22/06/18

Access to Document

10.1109/VLSIT.2018.8510705

Cite this

Vandooren, A., Franco, J., Parvais, B., Wu, Z., Witters, L., Walke, A., Li, W., Peng, L., Desphande, V., Bufler, F. M., Rassoul, N., Hellings, G., Jamieson, G., Inoue, F., Verbinnen, G., Devriendt, K., Teugels, L., Heylen, N., Vecchio, E., ... Collaert, N. (2018). 3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability. In 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018 (pp. 69-70). Article 8510705 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2018-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.2018.8510705

Vandooren, A. ; Franco, J. ; Parvais, B. et al. / 3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability. 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 69-70 (Digest of Technical Papers - Symposium on VLSI Technology).

@inproceedings{499c196e03e34cc9ab3eb1ff54a34183,

title = "3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability",

abstract = "3D sequential integration requires top MOSFETs processed at low thermal budget, which can impair the device reliability. In this work, top junction-less device are fabricated with a maximum processing temperature of 525°C. The devices feature high k /metal replacement gate and low temperature Si:P and SiGe:B 60\% raised SD for NMOS and PMOS respectively. Device matching, analog and RF performance of the top tier devices are in-line with state-of-the-art Si technology processed at high temperature (>1000°C). The top Si layer is transferred on CMOS planar bulk wafers with W metal-1 interconnects, using a SiCN to SiCN direct wafer bonding.",

author = "A. Vandooren and J. Franco and B. Parvais and Z. Wu and L. Witters and A. Walke and W. Li and L. Peng and V. Desphande and Bufler, \{F. M.\} and N. Rassoul and G. Hellings and G. Jamieson and F. Inoue and G. Verbinnen and K. Devriendt and L. Teugels and N. Heylen and E. Vecchio and T. Zheng and E. Rosseel and W. Vanherle and A. Hikavyy and Chan, \{B. T.\} and R. Ritzenthaler and G. Besnard and W. Schwarzenbach and G. Gaudin and I. Radu and Nguyen, \{B. Y.\} and N. Waldron and Heyn, \{V. De\} and D. Mocuta and N. Collaert",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018 ; Conference date: 18-06-2018 Through 22-06-2018",

year = "2018",

month = oct,

day = "25",

doi = "10.1109/VLSIT.2018.8510705",

language = "English",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "69--70",

booktitle = "2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018",

address = "United States",

}

Vandooren, A, Franco, J, Parvais, B, Wu, Z, Witters, L, Walke, A, Li, W, Peng, L, Desphande, V, Bufler, FM, Rassoul, N, Hellings, G, Jamieson, G, Inoue, F, Verbinnen, G, Devriendt, K, Teugels, L, Heylen, N, Vecchio, E, Zheng, T, Rosseel, E, Vanherle, W, Hikavyy, A, Chan, BT, Ritzenthaler, R, Besnard, G, Schwarzenbach, W, Gaudin, G, Radu, I, Nguyen, BY, Waldron, N, Heyn, VD, Mocuta, D & Collaert, N 2018, 3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability. in 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018., 8510705, Digest of Technical Papers - Symposium on VLSI Technology, vol. 2018-June, Institute of Electrical and Electronics Engineers Inc., pp. 69-70, 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018, Honolulu, United States, 18/06/18. https://doi.org/10.1109/VLSIT.2018.8510705

3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability. / Vandooren, A.; Franco, J.; Parvais, B. et al.
2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 69-70 8510705 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2018-June).

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

TY - GEN

T1 - 3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability

AU - Vandooren, A.

AU - Franco, J.

AU - Parvais, B.

AU - Wu, Z.

AU - Witters, L.

AU - Walke, A.

AU - Li, W.

AU - Peng, L.

AU - Desphande, V.

AU - Bufler, F. M.

AU - Rassoul, N.

AU - Hellings, G.

AU - Jamieson, G.

AU - Inoue, F.

AU - Verbinnen, G.

AU - Devriendt, K.

AU - Teugels, L.

AU - Heylen, N.

AU - Vecchio, E.

AU - Zheng, T.

AU - Rosseel, E.

AU - Vanherle, W.

AU - Hikavyy, A.

AU - Chan, B. T.

AU - Ritzenthaler, R.

AU - Besnard, G.

AU - Schwarzenbach, W.

AU - Gaudin, G.

AU - Radu, I.

AU - Nguyen, B. Y.

AU - Waldron, N.

AU - Heyn, V. De

AU - Mocuta, D.

AU - Collaert, N.

PY - 2018/10/25

Y1 - 2018/10/25

N2 - 3D sequential integration requires top MOSFETs processed at low thermal budget, which can impair the device reliability. In this work, top junction-less device are fabricated with a maximum processing temperature of 525°C. The devices feature high k /metal replacement gate and low temperature Si:P and SiGe:B 60% raised SD for NMOS and PMOS respectively. Device matching, analog and RF performance of the top tier devices are in-line with state-of-the-art Si technology processed at high temperature (>1000°C). The top Si layer is transferred on CMOS planar bulk wafers with W metal-1 interconnects, using a SiCN to SiCN direct wafer bonding.

AB - 3D sequential integration requires top MOSFETs processed at low thermal budget, which can impair the device reliability. In this work, top junction-less device are fabricated with a maximum processing temperature of 525°C. The devices feature high k /metal replacement gate and low temperature Si:P and SiGe:B 60% raised SD for NMOS and PMOS respectively. Device matching, analog and RF performance of the top tier devices are in-line with state-of-the-art Si technology processed at high temperature (>1000°C). The top Si layer is transferred on CMOS planar bulk wafers with W metal-1 interconnects, using a SiCN to SiCN direct wafer bonding.

UR - https://www.scopus.com/pages/publications/85055464487

U2 - 10.1109/VLSIT.2018.8510705

DO - 10.1109/VLSIT.2018.8510705

M3 - Conference proceeding

AN - SCOPUS:85055464487

T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - 69

EP - 70

BT - 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 38th IEEE Symposium on VLSI Technology, VLSI Technology 2018

Y2 - 18 June 2018 through 22 June 2018

ER -

Vandooren A, Franco J, Parvais B, Wu Z, Witters L, Walke A et al. 3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability. In 2018 IEEE Symposium on VLSI Technology, VLSI Technology 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 69-70. 8510705. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSIT.2018.8510705

3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability

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