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3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525°C with improved reliability

  • A. Vandooren
  • , J. Franco
  • , B. Parvais
  • , Z. Wu
  • , L. Witters
  • , A. Walke
  • , W. Li
  • , L. Peng
  • , V. Desphande
  • , F. M. Bufler
  • , N. Rassoul
  • , G. Hellings
  • , G. Jamieson
  • , F. Inoue
  • , G. Verbinnen
  • , K. Devriendt
  • , L. Teugels
  • , N. Heylen
  • , E. Vecchio
  • , T. Zheng
    • E. Rosseel, W. Vanherle, A. Hikavyy, B. T. Chan, R. Ritzenthaler, G. Besnard, W. Schwarzenbach, G. Gaudin, I. Radu, B. Y. Nguyen, N. Waldron, V. De Heyn, D. Mocuta, N. Collaert
  • Interuniversitair Micro-Elektronica Centrum
  • Vrije Universiteit Brussel
  • Swiss Federal Institute of Technology Zurich
  • Soitec S.A.

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

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