3D technologies for analog/RF applications

A. Vandooren; B. Parvais; L. Witters; A. Walke; A. Vais; C. Merckling; D. Lin; N. Waldron; P. Wambacq; D. Mocuta; N. Collaert

doi:10.1109/S3S.2017.8308746

3D technologies for analog/RF applications

A. Vandooren
, B. Parvais
, L. Witters
, A. Walke
, A. Vais
, C. Merckling
, D. Lin
, N. Waldron
, P. Wambacq
, D. Mocuta
, N. Collaert

Interuniversitair Micro-Elektronica Centrum

Research output: Chapter in Book/Report/Conference proceedings › Chapter › peer-review

Abstract

In this work, we will review possible technology options for next generation wireless communication. Next to the introduction of specific device architectures and materials, dissimilar from standard Si CMOS, the challenge will lie in the co-integration of these non-Si technologies with CMOS to enable power efficient systems with high performance, in this case high speed and output power, and reduced form factor. Next to monolithic integration, sequential 3D, currently been investigated for LOGIC density scaling, can be one of the enablers, allowing to combine technologies with very different needs at a finer grain and thus higher density than traditional 3D-SOC and 3D-IC technologies.

Original language	English
Title of host publication	2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1-3
Number of pages	3
ISBN (Electronic)	9781538637654
DOIs	https://doi.org/10.1109/S3S.2017.8308746
Publication status	Published - 2 Jul 2017
Externally published	Yes
Event	2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017 - Burlingame, United States Duration: 16 Oct 2017 → 18 Oct 2017

Publication series

Name	2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
Volume	2018-March

Conference

Conference	2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
Country/Territory	United States
City	Burlingame
Period	16/10/17 → 18/10/17

Keywords

III-V
monolithic integration
sequential 3D

Access to Document

10.1109/S3S.2017.8308746

Cite this

Vandooren, A., Parvais, B., Witters, L., Walke, A., Vais, A., Merckling, C., Lin, D., Waldron, N., Wambacq, P., Mocuta, D., & Collaert, N. (2017). 3D technologies for analog/RF applications. In 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017 (pp. 1-3). (2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017; Vol. 2018-March). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/S3S.2017.8308746

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title = "3D technologies for analog/RF applications",

abstract = "In this work, we will review possible technology options for next generation wireless communication. Next to the introduction of specific device architectures and materials, dissimilar from standard Si CMOS, the challenge will lie in the co-integration of these non-Si technologies with CMOS to enable power efficient systems with high performance, in this case high speed and output power, and reduced form factor. Next to monolithic integration, sequential 3D, currently been investigated for LOGIC density scaling, can be one of the enablers, allowing to combine technologies with very different needs at a finer grain and thus higher density than traditional 3D-SOC and 3D-IC technologies.",

keywords = "III-V, monolithic integration, sequential 3D",

author = "A. Vandooren and B. Parvais and L. Witters and A. Walke and A. Vais and C. Merckling and D. Lin and N. Waldron and P. Wambacq and D. Mocuta and N. Collaert",

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doi = "10.1109/S3S.2017.8308746",

language = "English",

series = "2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017",

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Vandooren, A, Parvais, B, Witters, L, Walke, A, Vais, A, Merckling, C, Lin, D, Waldron, N, Wambacq, P, Mocuta, D & Collaert, N 2017, 3D technologies for analog/RF applications. in 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, vol. 2018-March, Institute of Electrical and Electronics Engineers Inc., pp. 1-3, 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, Burlingame, United States, 16/10/17. https://doi.org/10.1109/S3S.2017.8308746

3D technologies for analog/RF applications. / Vandooren, A.; Parvais, B.; Witters, L. et al.
2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 1-3 (2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017; Vol. 2018-March).

Research output: Chapter in Book/Report/Conference proceedings › Chapter › peer-review

TY - CHAP

T1 - 3D technologies for analog/RF applications

AU - Vandooren, A.

AU - Parvais, B.

AU - Witters, L.

AU - Walke, A.

AU - Vais, A.

AU - Merckling, C.

AU - Lin, D.

AU - Waldron, N.

AU - Wambacq, P.

AU - Mocuta, D.

AU - Collaert, N.

PY - 2017/7/2

Y1 - 2017/7/2

N2 - In this work, we will review possible technology options for next generation wireless communication. Next to the introduction of specific device architectures and materials, dissimilar from standard Si CMOS, the challenge will lie in the co-integration of these non-Si technologies with CMOS to enable power efficient systems with high performance, in this case high speed and output power, and reduced form factor. Next to monolithic integration, sequential 3D, currently been investigated for LOGIC density scaling, can be one of the enablers, allowing to combine technologies with very different needs at a finer grain and thus higher density than traditional 3D-SOC and 3D-IC technologies.

AB - In this work, we will review possible technology options for next generation wireless communication. Next to the introduction of specific device architectures and materials, dissimilar from standard Si CMOS, the challenge will lie in the co-integration of these non-Si technologies with CMOS to enable power efficient systems with high performance, in this case high speed and output power, and reduced form factor. Next to monolithic integration, sequential 3D, currently been investigated for LOGIC density scaling, can be one of the enablers, allowing to combine technologies with very different needs at a finer grain and thus higher density than traditional 3D-SOC and 3D-IC technologies.

KW - III-V

KW - monolithic integration

KW - sequential 3D

UR - https://www.scopus.com/pages/publications/85047780033

U2 - 10.1109/S3S.2017.8308746

DO - 10.1109/S3S.2017.8308746

M3 - Chapter

AN - SCOPUS:85047780033

T3 - 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017

SP - 1

EP - 3

BT - 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017

Y2 - 16 October 2017 through 18 October 2017

ER -

Vandooren A, Parvais B, Witters L, Walke A, Vais A, Merckling C et al. 3D technologies for analog/RF applications. In 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 1-3. (2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017). doi: 10.1109/S3S.2017.8308746

3D technologies for analog/RF applications

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Keywords

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