A 1V 2mW 17GHz multi-modulus frequency divider based on TSPC logic using 65nm CMOS

Manthena Vamshi Krishna; Anil Jain; Nasir Abdul Quadir; Paul D. Townsend; Peter Ossieur

doi:10.1109/ESSCIRC.2014.6942114

A 1V 2mW 17GHz multi-modulus frequency divider based on TSPC logic using 65nm CMOS

Manthena Vamshi Krishna
, Anil Jain
, Nasir Abdul Quadir
, Paul D. Townsend
, Peter Ossieur

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

Abstract

We present a multi-modulus frequency divider based upon novel dual-modulus 4/5 and 2/3 true single-phase clocked (TSPC) prescalers. High-speed and low-power operation was achieved by merging the combinatorial counter logic with the flip-flop stages and removing circuit nodes at the expense of allowing a small short-circuit current during a short fraction of the operation cycle, thus minimizing the amount of nodes in the circuit. The divider is designed for operation in wireline or fibre-optic serial link transceivers with programmable divider ratios of 64, 80, 96, 100, 112, 120 and 140. The divider is implemented as part of a phase-locked loop around a quadrature voltage controlled oscillator in a 65nm CMOS technology. The maximum operating frequency is measured to be 17GHz with 2mW power consumption from a 1.0V supply voltage, and occupies 25×50μm².

Original language	English
Title of host publication	ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference
Editors	Pietro Andreani, Andrea Bevilacqua, Gaudenzio Meneghesso
Publisher	IEEE Computer Society
Pages	431-434
Number of pages	4
ISBN (Electronic)	9781479956944
DOIs	https://doi.org/10.1109/ESSCIRC.2014.6942114
Publication status	Published - 31 Oct 2014
Event	40th European Solid-State Circuit Conference, ESSCIRC 2014 - Venezia Lido, Italy Duration: 22 Sep 2014 → 26 Sep 2014

Publication series

Name	European Solid-State Circuits Conference
ISSN (Print)	1930-8833

Conference

Conference	40th European Solid-State Circuit Conference, ESSCIRC 2014
Country/Territory	Italy
City	Venezia Lido
Period	22/09/14 → 26/09/14

Keywords

frequency divider
Multi-modulus divider
prescaler
true single-phase clocked (TSPC) logic

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10.1109/ESSCIRC.2014.6942114

Cite this

Krishna, M. V., Jain, A., Quadir, N. A., Townsend, P. D., & Ossieur, P. (2014). A 1V 2mW 17GHz multi-modulus frequency divider based on TSPC logic using 65nm CMOS. In P. Andreani, A. Bevilacqua, & G. Meneghesso (Eds.), ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference (pp. 431-434). Article 6942114 (European Solid-State Circuits Conference). IEEE Computer Society. https://doi.org/10.1109/ESSCIRC.2014.6942114

Krishna, Manthena Vamshi ; Jain, Anil ; Quadir, Nasir Abdul et al. / A 1V 2mW 17GHz multi-modulus frequency divider based on TSPC logic using 65nm CMOS. ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference. editor / Pietro Andreani ; Andrea Bevilacqua ; Gaudenzio Meneghesso. IEEE Computer Society, 2014. pp. 431-434 (European Solid-State Circuits Conference).

@inproceedings{4aecb651bd254d538f991d36f5e6df87,

title = "A 1V 2mW 17GHz multi-modulus frequency divider based on TSPC logic using 65nm CMOS",

abstract = "We present a multi-modulus frequency divider based upon novel dual-modulus 4/5 and 2/3 true single-phase clocked (TSPC) prescalers. High-speed and low-power operation was achieved by merging the combinatorial counter logic with the flip-flop stages and removing circuit nodes at the expense of allowing a small short-circuit current during a short fraction of the operation cycle, thus minimizing the amount of nodes in the circuit. The divider is designed for operation in wireline or fibre-optic serial link transceivers with programmable divider ratios of 64, 80, 96, 100, 112, 120 and 140. The divider is implemented as part of a phase-locked loop around a quadrature voltage controlled oscillator in a 65nm CMOS technology. The maximum operating frequency is measured to be 17GHz with 2mW power consumption from a 1.0V supply voltage, and occupies 25×50μm2.",

keywords = "frequency divider, Multi-modulus divider, prescaler, true single-phase clocked (TSPC) logic",

author = "Krishna, \{Manthena Vamshi\} and Anil Jain and Quadir, \{Nasir Abdul\} and Townsend, \{Paul D.\} and Peter Ossieur",

note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 40th European Solid-State Circuit Conference, ESSCIRC 2014 ; Conference date: 22-09-2014 Through 26-09-2014",

year = "2014",

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doi = "10.1109/ESSCIRC.2014.6942114",

language = "English",

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}

Krishna, MV, Jain, A, Quadir, NA, Townsend, PD & Ossieur, P 2014, A 1V 2mW 17GHz multi-modulus frequency divider based on TSPC logic using 65nm CMOS. in P Andreani, A Bevilacqua & G Meneghesso (eds), ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference., 6942114, European Solid-State Circuits Conference, IEEE Computer Society, pp. 431-434, 40th European Solid-State Circuit Conference, ESSCIRC 2014, Venezia Lido, Italy, 22/09/14. https://doi.org/10.1109/ESSCIRC.2014.6942114

A 1V 2mW 17GHz multi-modulus frequency divider based on TSPC logic using 65nm CMOS. / Krishna, Manthena Vamshi; Jain, Anil; Quadir, Nasir Abdul et al.
ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference. ed. / Pietro Andreani; Andrea Bevilacqua; Gaudenzio Meneghesso. IEEE Computer Society, 2014. p. 431-434 6942114 (European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

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AU - Krishna, Manthena Vamshi

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AU - Quadir, Nasir Abdul

AU - Townsend, Paul D.

AU - Ossieur, Peter

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N2 - We present a multi-modulus frequency divider based upon novel dual-modulus 4/5 and 2/3 true single-phase clocked (TSPC) prescalers. High-speed and low-power operation was achieved by merging the combinatorial counter logic with the flip-flop stages and removing circuit nodes at the expense of allowing a small short-circuit current during a short fraction of the operation cycle, thus minimizing the amount of nodes in the circuit. The divider is designed for operation in wireline or fibre-optic serial link transceivers with programmable divider ratios of 64, 80, 96, 100, 112, 120 and 140. The divider is implemented as part of a phase-locked loop around a quadrature voltage controlled oscillator in a 65nm CMOS technology. The maximum operating frequency is measured to be 17GHz with 2mW power consumption from a 1.0V supply voltage, and occupies 25×50μm2.

AB - We present a multi-modulus frequency divider based upon novel dual-modulus 4/5 and 2/3 true single-phase clocked (TSPC) prescalers. High-speed and low-power operation was achieved by merging the combinatorial counter logic with the flip-flop stages and removing circuit nodes at the expense of allowing a small short-circuit current during a short fraction of the operation cycle, thus minimizing the amount of nodes in the circuit. The divider is designed for operation in wireline or fibre-optic serial link transceivers with programmable divider ratios of 64, 80, 96, 100, 112, 120 and 140. The divider is implemented as part of a phase-locked loop around a quadrature voltage controlled oscillator in a 65nm CMOS technology. The maximum operating frequency is measured to be 17GHz with 2mW power consumption from a 1.0V supply voltage, and occupies 25×50μm2.

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PB - IEEE Computer Society

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Y2 - 22 September 2014 through 26 September 2014

ER -

Krishna MV, Jain A, Quadir NA, Townsend PD, Ossieur P. A 1V 2mW 17GHz multi-modulus frequency divider based on TSPC logic using 65nm CMOS. In Andreani P, Bevilacqua A, Meneghesso G, editors, ESSCIRC 2014 - Proceedings of the 40th European Solid-State Circuit Conference. IEEE Computer Society. 2014. p. 431-434. 6942114. (European Solid-State Circuits Conference). doi: 10.1109/ESSCIRC.2014.6942114

A 1V 2mW 17GHz multi-modulus frequency divider based on TSPC logic using 65nm CMOS

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