A 2 order 1 -bit complex switched capacitor sigma-delta ADC with 90dB SNDR in a 180kHz bandwidth

  • Alan Bannon
  • , Anthony Dunne
  • , Daniel O'Hare
  • , Matthew Miller
  • , Omid Oliaei

Research output: Chapter in Book/Report/Conference proceedingsChapterpeer-review

Abstract

A complex switched capacitor sigma-delta ADC is described. The ADC is used in the VLEF RX path of a GSM/GPRS/EDGE phone and has an SNDR of 90dB in a 180kHz bandwidth, with the VLIF centered at 123kHz. The use of a complex noise transfer function allows for a more optimal use of noise shaping. The ADC is 2nd order, 1-bit, with a sampling rate of 52MHz implemented in 90nm CMOS.

Original languageEnglish
Title of host publicationICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems
Pages136-139
Number of pages4
DOIs
Publication statusPublished - 2006
Externally publishedYes
EventICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems - Nice, France
Duration: 10 Dec 200613 Dec 2006

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Conference

ConferenceICECS 2006 - 13th IEEE International Conference on Electronics, Circuits and Systems
Country/TerritoryFrance
CityNice
Period10/12/0613/12/06

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