@inbook{87f527898ec14c4ab39ddbe86e13b33a,
title = "A 2MS/s, 11.22 ENOB, 3.2 Vpp-d SAR ADC with improved DNL and offset calculation",
abstract = "A 12-bit SAR ADC with an extended input range of 3.2 Vpp-d (±1.33 VREF) achieved through the use of an input sampling scaling technique, is presented. The circuit also includes a comparator offset compensation technique that results in a residual offset of less than 0.5 LSB. The ADC is implemented in a 0.13 μm CMOS process and achieves an SNDR of 69.3 dB and an SFDR of 79 dB without calibration, while consuming 0.9 mW, with a measured DNL of 1.2/-1.0 LSB and INL of 2.3/-2.2 LSB.",
keywords = "Analog-to-Digital Converters, capacitor segmentation, comparator offset, feedback control system, SAR",
author = "Sohail Asghar and Sohaib Afridi and Anu Pillai and Anita Schuler and \{De La Rosa\}, \{Jose M.\} and Ivan O'Connell",
note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 ; Conference date: 27-05-2018 Through 30-05-2018",
year = "2018",
month = apr,
day = "26",
doi = "10.1109/ISCAS.2018.8350955",
language = "English",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2018 IEEE International Symposium on Circuits and Systems, ISCAS 2018 - Proceedings",
address = "United States",
}