A 4th-Order Continuous-Time ΔΣ Modulator with Improved Clock Jitter Immunity using RTZ FIR DAC

Ian Assom; Gerardo Salgado; Daniel O'Hare; Ivan O'Connell; Keith A. O'Donoghue

doi:10.1109/ICECS.2018.8617899

A 4^th-Order Continuous-Time ΔΣ Modulator with Improved Clock Jitter Immunity using RTZ FIR DAC

Ian Assom
, Gerardo Salgado
, Daniel O'Hare
, Ivan O'Connell
, Keith A. O'Donoghue

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

Abstract

This paper highlights the influence of the main feedback DAC non-idealities affecting the performance of Continuous-Time Delta-Sigma Modulators (CTDSMs) in radio receiver Internet-of-Things (IoT) applications. It proposes the combination of the Return-To-Zero (RTZ) DAC pulse and Finite-Impulse-Response (FIR) DAC to have inherent Inter-Symbol-Interference immunity and reduced clock jitter sensitivity, which is crucial to meet the strict linearity and Signal-To-Noise-Distortion-Ratio (SNDR) requirements for integrated IoT radio receivers. The proposed design is validated through MATLAB® Simulink® simulations, showing that a 4th order single-bit CTDSM with RTZ + FIR DAC can achieve an SNDR performance only 3dB below the ideal even in the presence of 4.2 ps rms of clock jitter at 24 MHz sampling frequency in a 250 kHz signal bandwidth.

Original language	English
Title of host publication	2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	725-728
Number of pages	4
ISBN (Electronic)	9781538695623
DOIs	https://doi.org/10.1109/ICECS.2018.8617899
Publication status	Published - 2 Jul 2018
Event	25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018 - Bordeaux, France Duration: 9 Dec 2018 → 12 Dec 2018

Publication series

Name	2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018

Conference

Conference	25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018
Country/Territory	France
City	Bordeaux
Period	9/12/18 → 12/12/18

Keywords

Analog-to-Digital Conversion (ADC)
clock jitter
compensation
CTDSM
Excess Loop Delay (ELD)
ISI
radio receiver
return-to-zero finite impulse response (RTZ FIR) DAC

Access to Document

10.1109/ICECS.2018.8617899

Cite this

Assom, I., Salgado, G., O'Hare, D., O'Connell, I., & O'Donoghue, K. A. (2018). A 4^th-Order Continuous-Time ΔΣ Modulator with Improved Clock Jitter Immunity using RTZ FIR DAC. In 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018 (pp. 725-728). Article 8617899 (2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICECS.2018.8617899

Assom, Ian ; Salgado, Gerardo ; O'Hare, Daniel et al. / A 4^th-Order Continuous-Time ΔΣ Modulator with Improved Clock Jitter Immunity using RTZ FIR DAC. 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 725-728 (2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018).

@inproceedings{729cd31ee9ee4f998f52e9c76c728b81,

title = "A 4th-Order Continuous-Time ΔΣ Modulator with Improved Clock Jitter Immunity using RTZ FIR DAC",

abstract = "This paper highlights the influence of the main feedback DAC non-idealities affecting the performance of Continuous-Time Delta-Sigma Modulators (CTDSMs) in radio receiver Internet-of-Things (IoT) applications. It proposes the combination of the Return-To-Zero (RTZ) DAC pulse and Finite-Impulse-Response (FIR) DAC to have inherent Inter-Symbol-Interference immunity and reduced clock jitter sensitivity, which is crucial to meet the strict linearity and Signal-To-Noise-Distortion-Ratio (SNDR) requirements for integrated IoT radio receivers. The proposed design is validated through MATLAB{\textregistered} Simulink{\textregistered} simulations, showing that a 4th order single-bit CTDSM with RTZ + FIR DAC can achieve an SNDR performance only 3dB below the ideal even in the presence of 4.2 ps rms of clock jitter at 24 MHz sampling frequency in a 250 kHz signal bandwidth.",

keywords = "Analog-to-Digital Conversion (ADC), clock jitter, compensation, CTDSM, Excess Loop Delay (ELD), ISI, radio receiver, return-to-zero finite impulse response (RTZ FIR) DAC",

author = "Ian Assom and Gerardo Salgado and Daniel O'Hare and Ivan O'Connell and O'Donoghue, \{Keith A.\}",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018 ; Conference date: 09-12-2018 Through 12-12-2018",

year = "2018",

month = jul,

day = "2",

doi = "10.1109/ICECS.2018.8617899",

language = "English",

series = "2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "725--728",

booktitle = "2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018",

address = "United States",

}

Assom, I, Salgado, G , O'Hare, D, O'Connell, I & O'Donoghue, KA 2018, A 4^th-Order Continuous-Time ΔΣ Modulator with Improved Clock Jitter Immunity using RTZ FIR DAC. in 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018., 8617899, 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018, Institute of Electrical and Electronics Engineers Inc., pp. 725-728, 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018, Bordeaux, France, 9/12/18. https://doi.org/10.1109/ICECS.2018.8617899

A 4^th-Order Continuous-Time ΔΣ Modulator with Improved Clock Jitter Immunity using RTZ FIR DAC. / Assom, Ian; Salgado, Gerardo ; O'Hare, Daniel et al.
2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 725-728 8617899 (2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018).

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

TY - GEN

T1 - A 4th-Order Continuous-Time ΔΣ Modulator with Improved Clock Jitter Immunity using RTZ FIR DAC

AU - Assom, Ian

AU - Salgado, Gerardo

AU - O'Hare, Daniel

AU - O'Connell, Ivan

AU - O'Donoghue, Keith A.

PY - 2018/7/2

Y1 - 2018/7/2

N2 - This paper highlights the influence of the main feedback DAC non-idealities affecting the performance of Continuous-Time Delta-Sigma Modulators (CTDSMs) in radio receiver Internet-of-Things (IoT) applications. It proposes the combination of the Return-To-Zero (RTZ) DAC pulse and Finite-Impulse-Response (FIR) DAC to have inherent Inter-Symbol-Interference immunity and reduced clock jitter sensitivity, which is crucial to meet the strict linearity and Signal-To-Noise-Distortion-Ratio (SNDR) requirements for integrated IoT radio receivers. The proposed design is validated through MATLAB® Simulink® simulations, showing that a 4th order single-bit CTDSM with RTZ + FIR DAC can achieve an SNDR performance only 3dB below the ideal even in the presence of 4.2 ps rms of clock jitter at 24 MHz sampling frequency in a 250 kHz signal bandwidth.

AB - This paper highlights the influence of the main feedback DAC non-idealities affecting the performance of Continuous-Time Delta-Sigma Modulators (CTDSMs) in radio receiver Internet-of-Things (IoT) applications. It proposes the combination of the Return-To-Zero (RTZ) DAC pulse and Finite-Impulse-Response (FIR) DAC to have inherent Inter-Symbol-Interference immunity and reduced clock jitter sensitivity, which is crucial to meet the strict linearity and Signal-To-Noise-Distortion-Ratio (SNDR) requirements for integrated IoT radio receivers. The proposed design is validated through MATLAB® Simulink® simulations, showing that a 4th order single-bit CTDSM with RTZ + FIR DAC can achieve an SNDR performance only 3dB below the ideal even in the presence of 4.2 ps rms of clock jitter at 24 MHz sampling frequency in a 250 kHz signal bandwidth.

KW - Analog-to-Digital Conversion (ADC)

KW - clock jitter

KW - compensation

KW - CTDSM

KW - Excess Loop Delay (ELD)

KW - ISI

KW - radio receiver

KW - return-to-zero finite impulse response (RTZ FIR) DAC

UR - https://www.scopus.com/pages/publications/85062259309

U2 - 10.1109/ICECS.2018.8617899

DO - 10.1109/ICECS.2018.8617899

M3 - Conference proceeding

AN - SCOPUS:85062259309

T3 - 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018

SP - 725

EP - 728

BT - 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018

Y2 - 9 December 2018 through 12 December 2018

ER -

Assom I, Salgado G , O'Hare D, O'Connell I, O'Donoghue KA. A 4^th-Order Continuous-Time ΔΣ Modulator with Improved Clock Jitter Immunity using RTZ FIR DAC. In 2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 725-728. 8617899. (2018 25th IEEE International Conference on Electronics Circuits and Systems, ICECS 2018). doi: 10.1109/ICECS.2018.8617899