Abstract
This paper presents a 7-bit digital to phase converter (DPC) for high speed clock and data recovery (CDR) applications which is capable of generating multi-phase clocks at 7-GHz frequency. Fabricated in a standard 65-nm CMOS technology, the design introduces a modified phase interpolator (PI) and a quadrature phase corrector (QPC) to reduce the effect of the circuit imperfections on the DPC's resolution and linearity. Employing a 14-GHz quadrature reference clock, the DPC achieves DNL/INL of 0.7/6 LSB respectively while consuming 40.5 mW power from 1.05 V supply.
| Original language | English |
|---|---|
| Pages (from-to) | 3976-3988 |
| Number of pages | 13 |
| Journal | IEEE Transactions on Circuits and Systems |
| Volume | 69 |
| Issue number | 10 |
| DOIs | |
| Publication status | Published - 1 Oct 2022 |
Keywords
- clock and data recovery (CDR)
- Digital to phase converter (DPC)
- phase interpolator (PI)
- wireline and optical communication