A 'digital' 6-bit ADC in 0.25μm CMOS

C. Donovan; M. P. Flynn

A 'digital' 6-bit ADC in 0.25μm CMOS

C. Donovan
, M. P. Flynn

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University College Cork

Research output: Contribution to journal › Article › peer-review

Abstract

Traditionally, circuit designers have adopted analog techniques to overcome comparator offset in flash converters. These schemes usually have an adverse effect on area and power consumption, and more seriously do not scale easily to low voltage processes. We describe a digital technique, which removes the accuracy constraints from the comparators. With no analog matching requirements, the comparators can be small, fast and power efficient. A 6-bit prototype converter built in a standard 0.25μm digital CMOS process occupies 1.2mm² and dissipates 110mW from a 2.2V supply at 300Ms/s.

Original language	English
Pages (from-to)	145-148
Number of pages	4
Journal	Proceedings of the Custom Integrated Circuits Conference
Publication status	Published - 2001
Event	IEEE 2001 Custom Integrated Circuits Conference - San Diego, CA, United States Duration: 6 May 2001 → 9 May 2001

Cite this

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abstract = "Traditionally, circuit designers have adopted analog techniques to overcome comparator offset in flash converters. These schemes usually have an adverse effect on area and power consumption, and more seriously do not scale easily to low voltage processes. We describe a digital technique, which removes the accuracy constraints from the comparators. With no analog matching requirements, the comparators can be small, fast and power efficient. A 6-bit prototype converter built in a standard 0.25μm digital CMOS process occupies 1.2mm2 and dissipates 110mW from a 2.2V supply at 300Ms/s.",

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AU - Flynn, M. P.

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AB - Traditionally, circuit designers have adopted analog techniques to overcome comparator offset in flash converters. These schemes usually have an adverse effect on area and power consumption, and more seriously do not scale easily to low voltage processes. We describe a digital technique, which removes the accuracy constraints from the comparators. With no analog matching requirements, the comparators can be small, fast and power efficient. A 6-bit prototype converter built in a standard 0.25μm digital CMOS process occupies 1.2mm2 and dissipates 110mW from a 2.2V supply at 300Ms/s.

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SN - 0886-5930

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JF - Proceedings of the Custom Integrated Circuits Conference

T2 - IEEE 2001 Custom Integrated Circuits Conference

Y2 - 6 May 2001 through 9 May 2001

ER -

A 'digital' 6-bit ADC in 0.25μm CMOS

Abstract

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