@inbook{6bd291dc376c430b8bde95c25b6e5bbe,
title = "A Digitally Calibrated 1stOrder Noise Shaped SAR ADC in 28 nm CMOS",
abstract = "This paper proposes techniques to achieve lower thermal noise in the loop filters of NS SAR ADCs. An error feedback topology is used to build a more robust filter without integrators. A first order topology is chosen to reduce thermal noise and novel cascade of dynamic amplifiers are used to avoid the series switches on top-plate capacitor node of SAR ADC. On-chip digital calibration is used to enhance the performance of an ADC. A protoype of Noise Shape SAR ADC is fabricated in 28 nm CMOS technology to demonstrate these techniques. Measurements shows that the proposed architecture achieves SNDR and SFDR of 78.5 dB and 82.9 dB respectively.",
keywords = "ADC, Analog-to-Digital converter, Dynamic Amplifier, Error Feedback, Loop Filter, Noise shaping, SAR, Successive approximation regis-ter",
author = "Subhash Chevella and Salgado, \{Gerardo Molina\} and Armia Salib and Anita Schuler and Barry Cardiff and Ivan O'Connell and Daniel O'Hare",
note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 31st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2024 ; Conference date: 18-11-2024 Through 20-11-2024",
year = "2024",
doi = "10.1109/ICECS61496.2024.10848849",
language = "English",
series = "Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2024 31st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2024",
address = "United States",
}