A GF(24m) inverter and its application in a reconfigurable Tate pairing processor

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Abstract

This paper details an architecture for performing inversion in the field GF(24m), which is the field used in computing the Tate pairing on characteristic 2 supersingular elliptic curves. The inverter architecture is then used to improve the performance of a reconfigurable Tate pairing hardware accelerator. Implementation results for the improved processor on an FPGA are presented and compared to those of the basic processor without the inverter.

Original languageEnglish
Title of host publicationProceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006
Pages158-167
Number of pages10
DOIs
Publication statusPublished - 2006
Event2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006 - San Luis Potosi, Mexico
Duration: 20 Sep 200622 Sep 2006

Publication series

NameProceedings of the 2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006

Conference

Conference2006 IEEE International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006
Country/TerritoryMexico
CitySan Luis Potosi
Period20/09/0622/09/06

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