TY - GEN
T1 - A hardware wrapper for the SHA-3 hash algorithms
AU - Baldwin, B.
AU - Byrne, A.
AU - Lu, Liang
AU - Hamilton, M.
AU - Hanley, N.
AU - O'Neill, M.
AU - Marnane, W. P.
PY - 2010
Y1 - 2010
N2 - The second round of the NIST public competition is underway to find a new hash algorithm(s) for inclusion in the NIST Secure Hash Standard (SHA-3). Computational efficiency of the algorithms in hardware is to be addressed during the second round of the contest. For software implementations NIST specifies an application programming interface (API) along with reference implementation for each of the designs, thereby enabling quick and easy comparison and testing on software platforms, however no such specification was given for hardware analysis. In this paper we present a hardware wrapper interface which attempts to encompass all the competition entries (and indeed, hash algorithms in general) across any number of both FPGA and ASIC hardware platforms. This interface comprises communications and padding, and attempts to standardise the hashing algorithms to allow accurate and fair area, timing and power measurement between the different designs.
AB - The second round of the NIST public competition is underway to find a new hash algorithm(s) for inclusion in the NIST Secure Hash Standard (SHA-3). Computational efficiency of the algorithms in hardware is to be addressed during the second round of the contest. For software implementations NIST specifies an application programming interface (API) along with reference implementation for each of the designs, thereby enabling quick and easy comparison and testing on software platforms, however no such specification was given for hardware analysis. In this paper we present a hardware wrapper interface which attempts to encompass all the competition entries (and indeed, hash algorithms in general) across any number of both FPGA and ASIC hardware platforms. This interface comprises communications and padding, and attempts to standardise the hashing algorithms to allow accurate and fair area, timing and power measurement between the different designs.
UR - https://www.scopus.com/pages/publications/78649602880
U2 - 10.1049/cp.2010.0478
DO - 10.1049/cp.2010.0478
M3 - Conference proceeding
AN - SCOPUS:78649602880
SN - 9781849192521
T3 - IET Conference Publications
SP - 1
EP - 6
BT - IET Irish Signals and Systems Conference, ISSC 2010
T2 - IET Irish Signals and Systems Conference, ISSC 2010
Y2 - 23 June 2010 through 24 June 2010
ER -