@inbook{3801abe532d5451baba7f0656d89cf2c,
title = "A Low Power Programmable Switch Supply Dynamic Comparator",
abstract = "This paper introduces a programmable switch supply comparator that uses a programmable reservoir capacitor to achieve a reduced effective supply voltage during the decision phase. This comparator achieves up to 50\% power consumption reduction against the conventional dynamic comparator. Fabricated in 65nm CMOS, the silicon results of the PMOS-input programmable comparator show programmable power consumption and energy efficiency ranging from 2.7 - 4.1μW and 0.22 - 0.5pJ/conv, respectively. Similarly, the input-referred noise can be programmed from 100 - 180μVrms. Additionally, the power (energy efficiency) and input-referred noise can be programmed at any clock cycle, making this design an ideal solution for the two-comparator SAR ADC architecture.",
keywords = "coarse and fine comparator, Dynamic comparator, low-noise, low-power, offset, SAR, StrongARM latch",
author = "Madhan Venkatesh and Salgado, \{Gerardo Molina\} and McCarthy, \{Kevin G.\} and Ivan O'Connell",
note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024 ; Conference date: 19-05-2024 Through 22-05-2024",
year = "2024",
doi = "10.1109/ISCAS58744.2024.10558322",
language = "English",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "ISCAS 2024 - IEEE International Symposium on Circuits and Systems",
address = "United States",
}