A Point-to-Point Time-Optimal Dynamic Voltage Scaling for High-Performance Processor VRMs

Dynamic voltage scaling (DVS) is essential for improving energy efficiency in processor power supplies, but in server-class VRMs the multi-millifarad output capacitance severely restricts the achievable slew rate. Conventional digital controllers perform DVS by slewing the reference with fixed linear slopes, and to stay within current limits they must use conservative settings that both lengthen the transition and still allow considerable overshoot and undershoot. This paper presents a point-to-point, time-optimal DVS scheme for multiphase buck VRMs supplying high-performance processors. Exploiting the fact that the target voltage is known at the beginning of the transition, a large-signal model is derived that links the output-voltage trajectory to the ON/OFF intervals of all phases. Closed-form expressions are obtained for these intervals in both upward and downward DVS ramps, guaranteeing a soft landing at the target voltage with near-theoretical slew rate and negligible overshoot or undershoot. The same framework is used to estimate the peak inductor current and to derive a simple bound on the maximum single-step DVS amplitude, and larger transitions are automatically divided into multiple time-optimal sub-steps to avoid over-current protection. The scheme is implemented in a 1 MHz eight-phase VRM with 6.648 mF output capacitance. Compared with two state-of-the-art commercial controllers under identical hardware and nominal 30 mV/μs settings, the proposed controller maintains <10 mV fluctuation over 0.6-1.4 V and achieves up to 30 mV/μs effective slew rate, more than doubling the DVS speed.