A reconfigurable implementation of the tate pairing computation over GF(2m)

Research output: Chapter in Book/Report/Conference proceedingsChapterpeer-review

Abstract

In this paper the performance of a closed formula implemented in reconfigurable hardware for the Tate pairing Algorithm over the binary field of GF(2 m ) is studied. Using the algorithm improvement of Soonhak Kwon [2], the schedule for performing the Tate pairing without a square root operation is explored along with the area and time consumption trade-offs involved in the hardware implementation of the target algorithm.

Original languageEnglish
Title of host publicationReconfigurable Computing
Subtitle of host publicationArchitectures, Tools and Applications - 6th International Symposium, ARC 2010, Proceedings
Pages80-91
Number of pages12
DOIs
Publication statusPublished - 2010
Event6th International Symposium on Applied Reconfigurable Computing, ARC 2010 - Bangkok, Thailand
Duration: 17 Mar 201019 Mar 2010

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume5992 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

Conference6th International Symposium on Applied Reconfigurable Computing, ARC 2010
Country/TerritoryThailand
CityBangkok
Period17/03/1019/03/10

Keywords

  • FPGA implementation
  • Tate pairing

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