TY - GEN
T1 - A regular parallel multiplier which utilizes multiple carry-propagate adders
AU - Eriksson, Heizrik
AU - Larsson-Edefors, Per
AU - Marnane, William P.
PY - 2001
Y1 - 2001
N2 - A new regular partial-product reduction tree for parallel multipliers is presented in this paper. The reduction tree has a simple and efficient interconnect configuration and a minimal hardware usage. The reduction tree has a gate structure, which allows for extensive use of carry-propagation adders. Since carry-propagation adders can be very efficiently implemented, significant delay reduction is expected for large multipliers.
AB - A new regular partial-product reduction tree for parallel multipliers is presented in this paper. The reduction tree has a simple and efficient interconnect configuration and a minimal hardware usage. The reduction tree has a gate structure, which allows for extensive use of carry-propagation adders. Since carry-propagation adders can be very efficiently implemented, significant delay reduction is expected for large multipliers.
UR - https://www.scopus.com/pages/publications/84888032456
U2 - 10.1109/ISCAS.2001.922198
DO - 10.1109/ISCAS.2001.922198
M3 - Conference proceeding
AN - SCOPUS:84888032456
SN - 0780366859
SN - 9780780366855
T3 - ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
SP - 166
EP - 169
BT - ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
T2 - 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
Y2 - 6 May 2001 through 9 May 2001
ER -