Abstract
A new regular partial-product reduction tree for parallel multipliers is presented in this paper. The reduction tree has a simple and efficient interconnect configuration and a minimal hardware usage. The reduction tree has a gate structure, which allows for extensive use of carry-propagation adders. Since carry-propagation adders can be very efficiently implemented, significant delay reduction is expected for large multipliers.
| Original language | English |
|---|---|
| Pages (from-to) | IV166-IV169 |
| Journal | Materials Research Society Symposium - Proceedings |
| Volume | 626 |
| Publication status | Published - 2001 |
| Externally published | Yes |
| Event | Thermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications - San Francisco, CA, United States Duration: 24 Apr 2000 → 27 Apr 2000 |