A regular parallel multiplier which utilizes multiple carry-propagate adders

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Abstract

A new regular partial-product reduction tree for parallel multipliers is presented in this paper. The reduction tree has a simple and efficient interconnect configuration and a minimal hardware usage. The reduction tree has a gate structure, which allows for extensive use of carry-propagation adders. Since carry-propagation adders can be very efficiently implemented, significant delay reduction is expected for large multipliers.

Original languageEnglish
Pages (from-to)IV166-IV169
JournalMaterials Research Society Symposium - Proceedings
Volume626
Publication statusPublished - 2001
Externally publishedYes
EventThermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications - San Francisco, CA, United States
Duration: 24 Apr 200027 Apr 2000

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