A reversible MIPS multi-cycle control FSM design

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Abstract

Design of sequential circuits involves memory elements and combinational gates. The specification of these circuits is usually done by using the finite state machines. A microprocessor can be visualized as a large finite state machine. Thus it is a known fact that FSM design plays major role in specifying the sequential circuits. A reversible design of the infamous MIPS multi-cycle FSM is introduced in this paper. Three FSMs namely original, reverse and reversible FSM of the MIPS control circuit is designed, synthesized and simulated. Synthesis and simulation results are provided for the three implementations. The overhead for designing the reversible FSM areγ log2(N)γ conflict pins and one direction pin along with extra logic for inserting them.

Original languageEnglish
Title of host publication2009 1st Asia Symposium on Quality Electronic Design, ASQED 2009
Pages336-342
Number of pages7
DOIs
Publication statusPublished - 2009
Event2009 1st Asia Symposium on Quality Electronic Design, ASQED 2009 - Kuala Lumpur, Malaysia
Duration: 15 Jul 200916 Jul 2009

Publication series

Name2009 1st Asia Symposium on Quality Electronic Design, ASQED 2009

Conference

Conference2009 1st Asia Symposium on Quality Electronic Design, ASQED 2009
Country/TerritoryMalaysia
CityKuala Lumpur
Period15/07/0916/07/09

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