A study of capacitance-voltage hysteresis in the HfO₂/InGaAs metal-oxide-semiconductor system

In this work, we performed a study of capacitance-voltage (C-V) hysteresis in HfO₂/InGaAs metal-oxide-semiconductor (MOS) systems. The charge trapping density estimated from the C-V hysteresis is comparable to or even greater than the typical interface state density in high-k/InGaAs MOS systems. Based on an oxide thickness series, it is demonstrated that the magnitude of C-V hysteresis increases linearly with the increasing HfO₂ thickness, with the corresponding density of trapped charge being a constant value over the range of oxide thicknesses, indicating that the charge trapping is occurring in a plane near/at the HfO₂/InGaAs interfacial transition region. C-V hysteresis with a hold in accumulation was also investigated. It is observed that the C-V hysteresis has a power law dependence on the stress time in accumulation at the initial stage of stressing and tends to reach a plateau for sufficiently long stress times. Moreover, a larger gate voltage used during the stress increases the oxide field, allowing more border traps to be accessed.