TY - CHAP
T1 - A supply voltage-dependent variation aware reliability evaluation model
AU - Yang, Bo
AU - Popovici, Emanuel
AU - Quille, Michael Alan
AU - Amann, Andreas
AU - Cotofana, Sorin
N1 - Publisher Copyright:
© 2016 ACM.
PY - 2016/9/14
Y1 - 2016/9/14
N2 - With the continuous scaling of CMOS VLSI technology well into the nano-meter regime, and the increasing demand for ultra low power/low voltage circuits and systems, reliability is becoming an extra design optimisation goal in addition to size, performance, and energy. In this paper, a supply voltage (Vdd-) dependent, transistor threshold voltage variation aware propagation delay estimation model and a comprehensive statistical model to evaluate the reliability of the VLSI circuits is proposed. This accurate Vdd-dependent reliability evaluation model can be applied in the process of reliability driven multi-objective optimisation, which deals with tradeoffs between reliability, area, performance and energy. The experimental results show that the average estimation error is within 3% when compared to Monte-Carlo SPICE simulation while saving runtime by at least 100 times for generic benchmark circuits.
AB - With the continuous scaling of CMOS VLSI technology well into the nano-meter regime, and the increasing demand for ultra low power/low voltage circuits and systems, reliability is becoming an extra design optimisation goal in addition to size, performance, and energy. In this paper, a supply voltage (Vdd-) dependent, transistor threshold voltage variation aware propagation delay estimation model and a comprehensive statistical model to evaluate the reliability of the VLSI circuits is proposed. This accurate Vdd-dependent reliability evaluation model can be applied in the process of reliability driven multi-objective optimisation, which deals with tradeoffs between reliability, area, performance and energy. The experimental results show that the average estimation error is within 3% when compared to Monte-Carlo SPICE simulation while saving runtime by at least 100 times for generic benchmark circuits.
KW - Delay Estimation
KW - Delay PDF Propagation
KW - Reliability
KW - Statistical Timing Analysis
KW - VLSI
UR - https://www.scopus.com/pages/publications/84992107961
U2 - 10.1145/2950067.2950089
DO - 10.1145/2950067.2950089
M3 - Chapter
AN - SCOPUS:84992107961
T3 - Proceedings of the 2016 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016
SP - 79
EP - 84
BT - Proceedings of the 2016 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016
PB - Presses Polytechniques Et Universitaires Romandes
T2 - 2016 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016
Y2 - 18 July 2016 through 20 July 2016
ER -