TY - GEN
T1 - A versatile digital pulsewidth modulation architecture with area-Eficient FPGA implementation
AU - Foley, Raymond F.
AU - Kavanagh, Richard C.
AU - Marnane, William P.
AU - Egan, Michael G.
PY - 2005
Y1 - 2005
N2 - This paper describes a multi-output digital pulsewidth modulator (DPWM) that generates versatile waveforms suitable for use in a typical multi-phase interleaved switching dc-dc buck converter. A heterogenous DPWM is proposed that achieves a resolution of 255 ps, facilitating multi-megahertz switching frequencies. A novel global architecture is also introduced that exploits the phased nature of the interleaved buck converter, limiting the number of required multiplexers/comparators and enabling a large, adjustable number of variable-frequency pulsewidth modulated outputs to be generated using a small, xed architecture with programmable duty-cycles and dead-times.
AB - This paper describes a multi-output digital pulsewidth modulator (DPWM) that generates versatile waveforms suitable for use in a typical multi-phase interleaved switching dc-dc buck converter. A heterogenous DPWM is proposed that achieves a resolution of 255 ps, facilitating multi-megahertz switching frequencies. A novel global architecture is also introduced that exploits the phased nature of the interleaved buck converter, limiting the number of required multiplexers/comparators and enabling a large, adjustable number of variable-frequency pulsewidth modulated outputs to be generated using a small, xed architecture with programmable duty-cycles and dead-times.
UR - https://www.scopus.com/pages/publications/33847733596
U2 - 10.1109/PESC.2005.1582001
DO - 10.1109/PESC.2005.1582001
M3 - Conference proceeding
AN - SCOPUS:33847733596
SN - 0780390334
SN - 9780780390331
T3 - PESC Record - IEEE Annual Power Electronics Specialists Conference
SP - 2609
EP - 2615
BT - 36th IEEE Power Electronics Specialists Conference 2005
ER -