Adaptable-delay balanced-loss binary photonic delay line architectures using polarization switching

A photonic delay line (PDL) architecture that gives balanced loss switched states is proposed and demonstrated. This balanced loss performance leads to balanced optical signal flow through the delay line, as is critically required in many signal processing applications. The balanced PDL module design also provides efficient usage of optical power. This module is based on a compact reflective and symmetric optical layout geometry. It is also adjustable to a wide range of time delays, from subpicoseconds to tens of nanoseconds, hence the adaptable nature of hardware. Theoretical analysis as well as experiments are performed to make comparisons with the previously demonstrated reflective PDL architecture. Issues such as electrical signal-to-noise ratio and relative output signal power between the two PDL settings are discussed. In addition to the new adaptable delay balanced loss PDL, two novel hardware compression techniques based on wavelength multiplexing and polarization multiplexing are proposed that can be used with the adaptable PDL architecture to realize multichannel PDLs.