Advanced FinFET devices for sub-32nm technology nodes: Characteristics and integration challenges

  • A. Veloso
  • , N. Collaert
  • , A. De Keersgieter
  • , L. Witters
  • , R. Rooyackers
  • , M. J.H. Van Dal
  • , R. Duffy
  • , B. J. Pawlak
  • , R. J.P. Lander
  • , T. Hoffmann
  • , S. Biesemans
  • , M. Jurczak

Research output: Chapter in Book/Report/Conference proceedingsConference proceedingpeer-review

Abstract

We report a comprehensive evaluation and overview of the latest developments and technology challenges of FinFET-based devices. They offer improved electrostatics and steeper sub-threshold slopes, attractive for enabling further CMOS scaling, but can also suffer from higher parasitic resistance and parasitic capacitance for narrow Fin devices. Critical solutions to minimize the impact of the latter are here addressed, demonstrating their viability for replacing planar CMOS devices. Multiple-VT CMOS can be achieved with capping technology, with aggressively scaled Ring Oscillators (RO) and SRAM cells showing excellent performance and matching behavior.

Original languageEnglish
Title of host publicationECS Transactions - Silicon-on-Insulator Technology and Devices 14 - 215th Meeting of the Electrochemical Society
PublisherElectrochemical Society Inc.
Pages45-54
Number of pages10
Edition4
ISBN (Electronic)9781607680628
ISBN (Print)9781566777124
DOIs
Publication statusPublished - 2009
Externally publishedYes
Event14th International Symposium on Silicon-On-Insulator Technology and Devices - 215th Meeting of the Electrochemical Society - San Francisco, CA, United States
Duration: 24 May 200929 May 2009

Publication series

NameECS Transactions
Number4
Volume19
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Conference

Conference14th International Symposium on Silicon-On-Insulator Technology and Devices - 215th Meeting of the Electrochemical Society
Country/TerritoryUnited States
CitySan Francisco, CA
Period24/05/0929/05/09

Fingerprint

Dive into the research topics of 'Advanced FinFET devices for sub-32nm technology nodes: Characteristics and integration challenges'. Together they form a unique fingerprint.

Cite this