Abstract
In 1993 the flash EEPROM share of the memory market increased by 73%, establishing it as the fastest growing segment of the non-volatile memory market [1]. The aim of this work is to develop and integrate a flash EEPROM memory module into an existing CMOS process without compromising its performance. A design methodology is presented which demonstrates the use of numerical simulation in the evaluation of different process options, before committing the design to silicon.
| Original language | English |
|---|---|
| Pages (from-to) | 14/1-14/6 |
| Journal | IEE Colloquium (Digest) |
| Issue number | 33 |
| Publication status | Published - 1995 |
| Event | IEE Electronics Division Colloquium on Advanced MOS and BI-Polar Devices - London, UK Duration: 14 Feb 1995 → 14 Feb 1995 |
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