Algorithms and architectures for use in FPGA implementations of Identity Based Encryption schemes

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Abstract

In this paper algorithms and architectures for new GF(3m) multiplier and inverter components are presented. It is described how they can be utilized as part of a hardware implementation of an Identity Based Encryption (IBE) scheme. The main computation, the Tate pairing in such a scheme in outlined and it is illustrated how it can be implemented on reconfigurable hardware using these components.

Original languageEnglish
Title of host publicationLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
EditorsJurgen Becker, Marco Platzner, Serge Vernalde
PublisherSpringer Verlag
Pages74-83
Number of pages10
ISBN (Print)3540229892, 9783540229896
DOIs
Publication statusPublished - 2004

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume3203
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

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