An approach for digital Circuit Error/Reliability Propagation Analysis based on Conditional Probability

The continuous transistor scaling and extremely lower power constraints in modern VLSI chips can potentially supersede the benefits of the technology shrinking due to reliability issues. Due to external aggression factors, e.g., radiation and temperature gradients, the CMOS devices flawless functioning cannot be guaranteed any more. Thus, design time Integrated Circuits (ICs) reliability assessment is now turning out to be a mandatory step in the IC design flow. In this work, we present a novel CAD analytical error/reliability propagation analysis technique called Conditional Probabilistic Error/Reliability Propagation Analysis (CPERPA) algorithm. CPERPA efficiently resolves reliability related correlations including reconvergent fanouts and related errors, using a condition algorithm originating from the conditional probability theory, which promotes the accuracy at the expense of relatively low complexity enhancement. Experimental results on several benchmark circuits demonstrate the accuracy and the simulation time advantages of our approach when compared to Monte-Carlo simulations. The results obtained with the proposed CPERPA framework are within 3% average error and up to 1000 times faster when compared to Monte-Carlo simulations.