An area-efficient digital pulsewidth modulation architecture suitable for FPGA implementation

Raymond F. Foley; Richard C. Kavanagh; William P. Marnane; Michael G. Egan

doi:10.1109/APEC.2005.1453214

An area-efficient digital pulsewidth modulation architecture suitable for FPGA implementation

Raymond F. Foley
, Richard C. Kavanagh
, William P. Marnane
, Michael G. Egan

University College Cork

Research output: Contribution to conference › Paper › peer-review

Abstract

This paper describes a digital pulse width modulator (DPWM) designed for FPGA implementation. A novel multi-output pulsewidth modulation scheme is introduced, as is a frequency calibration method suitable for use on FPGAs. The resulting architecture provides versatile output waveforms with high resolution, but with a small area requirement.

Original language	English
Pages	1412-1418
Number of pages	7
DOIs	https://doi.org/10.1109/APEC.2005.1453214
Publication status	Published - 2005
Event	20th Annual IEEEApplied Power ElectronicsConference and Exposition, APEC 2005 - Austin, TX, United States Duration: 6 Mar 2005 → 10 Mar 2005

Conference

Conference	20th Annual IEEEApplied Power ElectronicsConference and Exposition, APEC 2005
Country/Territory	United States
City	Austin, TX
Period	6/03/05 → 10/03/05

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10.1109/APEC.2005.1453214

Cite this

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title = "An area-efficient digital pulsewidth modulation architecture suitable for FPGA implementation",

abstract = "This paper describes a digital pulse width modulator (DPWM) designed for FPGA implementation. A novel multi-output pulsewidth modulation scheme is introduced, as is a frequency calibration method suitable for use on FPGAs. The resulting architecture provides versatile output waveforms with high resolution, but with a small area requirement.",

author = "Foley, \{Raymond F.\} and Kavanagh, \{Richard C.\} and Marnane, \{William P.\} and Egan, \{Michael G.\}",

year = "2005",

doi = "10.1109/APEC.2005.1453214",

language = "English",

pages = "1412--1418",

note = "20th Annual IEEEApplied Power ElectronicsConference and Exposition, APEC 2005 ; Conference date: 06-03-2005 Through 10-03-2005",

}

An area-efficient digital pulsewidth modulation architecture suitable for FPGA implementation. / Foley, Raymond F.; Kavanagh, Richard C.; Marnane, William P. et al.
2005. 1412-1418 Paper presented at 20th Annual IEEEApplied Power ElectronicsConference and Exposition, APEC 2005, Austin, TX, United States.

Research output: Contribution to conference › Paper › peer-review

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T1 - An area-efficient digital pulsewidth modulation architecture suitable for FPGA implementation

AU - Foley, Raymond F.

AU - Kavanagh, Richard C.

AU - Marnane, William P.

AU - Egan, Michael G.

PY - 2005

Y1 - 2005

N2 - This paper describes a digital pulse width modulator (DPWM) designed for FPGA implementation. A novel multi-output pulsewidth modulation scheme is introduced, as is a frequency calibration method suitable for use on FPGAs. The resulting architecture provides versatile output waveforms with high resolution, but with a small area requirement.

AB - This paper describes a digital pulse width modulator (DPWM) designed for FPGA implementation. A novel multi-output pulsewidth modulation scheme is introduced, as is a frequency calibration method suitable for use on FPGAs. The resulting architecture provides versatile output waveforms with high resolution, but with a small area requirement.

UR - https://www.scopus.com/pages/publications/33646506301

U2 - 10.1109/APEC.2005.1453214

DO - 10.1109/APEC.2005.1453214

M3 - Paper

AN - SCOPUS:33646506301

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T2 - 20th Annual IEEEApplied Power ElectronicsConference and Exposition, APEC 2005

Y2 - 6 March 2005 through 10 March 2005

ER -

An area-efficient digital pulsewidth modulation architecture suitable for FPGA implementation

Abstract

Conference

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