An enhanced constant sample-time digital tachometer through oversampling

High-quality digital tachometers are incorporated into servo, mechatronic, robotic and precision production systems for the calculation of accurate, high-bandwidth, digital velocity information. The M/T-type tachometer and the related constant sample-time digital tachometer (CSDT) have been shown to perform well in many such systems. However, sensor nonideality can introduce very significant errors into the tachometer output. In this paper, it is shown that performance can be greatly improved (i.e., the noise present in the velocity signal significantly reduced) by oversampling the counter values used for velocity calculation. The counting and oversampling operations inherent to the oversampled CSDT (OCSDT) are implemented using a field-programmable gate array (FPGA). The design of the digital circuitry is described in detail, with particular emphasis on the circuits required for implementation and control of the oversampling operation. The FPGA acts as a peripheral device to a digital signal processor (DSP). Besides implementing some division-based calculations to generate a velocity word, the DSP can carry out other measurement and control functions, as required by the overall system. Simulation studies and experimental results are used to highlight the advantages of the over-sampling technique.