An enhanced constant sample-time digital tachometer through oversampling

High-quality digital tachometers, such as the M/T-type tachometer and constant sample-time digital tachometer (CSDT), are incorporated into many mechatronic control and measurement systems for the calculation of accurate digital velocity information. However, sensor non-ideality can introduce very significant errors into the output of these devices. In this paper, it is shown that performance can be greatly improved by oversampling the counter values used for velocity calculation. The counting and oversampling operations inherent to the oversampled CSDT (OCSDT) are implemented using a field-programmable gate array (FPGA). The design of the digital circuitry is described. Experimental results are used to highlight the advantages of the new device.