Architecture and implementation of a distributed reconfigurable metacomputer

Research output: Chapter in Book/Report/Conference proceedingsChapterpeer-review

Abstract

The use of application-specific co-processors created using reconfigurable hardware (FPGAs) has been shown to realize significant speed increases for many computationally intensive applications. The addition of reconfigurable hardware to clusters composed of commodity machines in order to improve the execution times of parallel applications would, therefore, appear to be a logical step. However, the extra complications introduced by this technique may make the real-world application of such technology appear to be prohibitively difficult. In this paper the design and implementation of a metacomputer designed to simplify the development of applications for clusters containing reconfigurable hardware are presented. The operation of the metacomputer is also discussed in some detail, including the process of implementing applications for execution on the metacomputer.

Original languageEnglish
Title of host publicationProceedings - 2nd International Symposium on Parallel and Distributed Computing, ISPDC 2003
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages153-158
Number of pages6
ISBN (Electronic)0769520693, 9780769520698
DOIs
Publication statusPublished - 2003
Event2nd International Symposium on Parallel and Distributed Computing, ISPDC 2003 - Ljubljana, Slovenia
Duration: 13 Oct 200314 Oct 2003

Publication series

NameProceedings - 2nd International Symposium on Parallel and Distributed Computing, ISPDC 2003

Conference

Conference2nd International Symposium on Parallel and Distributed Computing, ISPDC 2003
Country/TerritorySlovenia
CityLjubljana
Period13/10/0314/10/03

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