TY - GEN
T1 - Atomic scale simulation of a junctionless silicon nanowire transistor
AU - Ansari, Lida
AU - Feldman, Baruch
AU - Fagas, Giorgos
AU - Colinge, Jean Pierre
AU - Greer, James C.
PY - 2011
Y1 - 2011
N2 - We have simulated silicon nanowire junctionless transistors with a 3 nm gate length within a Density Functional Theory (DFT) framework. We explored the response of transistors to source-drain bias, VDS, and gate voltage, Vg. Also, the effect of bulk and surface adatom in the wire cross section was evaluated.
AB - We have simulated silicon nanowire junctionless transistors with a 3 nm gate length within a Density Functional Theory (DFT) framework. We explored the response of transistors to source-drain bias, VDS, and gate voltage, Vg. Also, the effect of bulk and surface adatom in the wire cross section was evaluated.
UR - https://www.scopus.com/pages/publications/79957988885
U2 - 10.1109/ULIS.2011.5757976
DO - 10.1109/ULIS.2011.5757976
M3 - Conference proceeding
AN - SCOPUS:79957988885
SN - 9781457700903
T3 - 2011 12th International Conference on Ultimate Integration on Silicon, ULIS 2011
SP - 96
EP - 98
BT - 2011 12th International Conference on Ultimate Integration on Silicon, ULIS 2011
T2 - 2011 12th International Conference on Ultimate Integration on Silicon, ULIS 2011
Y2 - 14 March 2011 through 16 March 2011
ER -