TY - GEN
T1 - Automatic optimization techniques for formal verification of asynchronous circuits
AU - Boubekeur, M.
AU - Schellekens, M. P.
PY - 2007
Y1 - 2007
N2 - Even medium size asynchronous circuits may display a complex behavior, due to the combinational explosion in the chronology of events that may happen. It is thus essential to apply automatic optimization techniques to avoid such complexity when formally verifying the correctness of the circuit. This paper presents dedicated techniques for optimization of formal verification of asynchronous circuits, these include for instance: automata reduction, pre-order reduction and automatic abstraction. All these techniques have been implemented and tested in a formal verification environment.
AB - Even medium size asynchronous circuits may display a complex behavior, due to the combinational explosion in the chronology of events that may happen. It is thus essential to apply automatic optimization techniques to avoid such complexity when formally verifying the correctness of the circuit. This paper presents dedicated techniques for optimization of formal verification of asynchronous circuits, these include for instance: automata reduction, pre-order reduction and automatic abstraction. All these techniques have been implemented and tested in a formal verification environment.
UR - https://www.scopus.com/pages/publications/50649106196
U2 - 10.1109/ICECS.2007.4510985
DO - 10.1109/ICECS.2007.4510985
M3 - Conference proceeding
AN - SCOPUS:50649106196
SN - 1424413788
SN - 9781424413782
T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
SP - 283
EP - 286
BT - ICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems
T2 - 14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007
Y2 - 11 December 2007 through 14 December 2007
ER -