TY - GEN
T1 - Back-gate mirror doping for fully depleted planar SOI transistors with thin buried oxide
AU - Yan, Ran
AU - Duane, Russell
AU - Razavi, Pedram
AU - Afzalian, Aryan
AU - Ferain, Isabelle
AU - Lee, Chi Woo
AU - Dehdashti, Nima
AU - Nguyen, Bich Yen
AU - Bourdelle, Konstantin K.
AU - Colinge, J. P.
PY - 2010
Y1 - 2010
N2 - In this paper, we analyze LDD depletion effects in Fully-Depleted SOI (FDSOI) devices with thin-BOX and ground plane (GP). Back-gate engineering is introduced to reduce the channel effects are rather insensitive to SOI layer thickness variations and remains well controlled for gate lengths down to 15nm.
AB - In this paper, we analyze LDD depletion effects in Fully-Depleted SOI (FDSOI) devices with thin-BOX and ground plane (GP). Back-gate engineering is introduced to reduce the channel effects are rather insensitive to SOI layer thickness variations and remains well controlled for gate lengths down to 15nm.
KW - Back-gate engineering
KW - Fully depleted silicon-on-insulation (FDSOI) MOSFET
KW - LDD depletion effect
KW - Thin buried-oxided (BOX)
UR - https://www.scopus.com/pages/publications/77957922387
U2 - 10.1109/VTSA.2010.5488939
DO - 10.1109/VTSA.2010.5488939
M3 - Conference proceeding
AN - SCOPUS:77957922387
SN - 9781424450633
T3 - Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010
SP - 76
EP - 77
BT - Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010
T2 - 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010
Y2 - 26 April 2010 through 28 April 2010
ER -