Bit-serial interleaved high speed division

W. P. Marnane; S. J. Bellis; P. Larsson-Edefors

doi:10.1049/el:19970758

Bit-serial interleaved high speed division

W. P. Marnane
, S. J. Bellis
, P. Larsson-Edefors

Research output: Contribution to journal › Article › peer-review

Abstract

A bit-serial/word-parallel divider circuit with simplified control requirements, is presented. The circuit uses the non-restoring division algorithm which places a restriction on the speed of the circuit. By introducing the concept of bit interleaving, a high speed design can be implemented of the same circuit complexity as an equivalent size multiplier.

Original language	English
Pages (from-to)	1124-1125
Number of pages	2
Journal	Electronics Letters
Volume	33
Issue number	13
DOIs	https://doi.org/10.1049/el:19970758
Publication status	Published - 19 Jun 1997

Keywords

Dividing circuits
VLSI

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10.1049/el:19970758

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title = "Bit-serial interleaved high speed division",

abstract = "A bit-serial/word-parallel divider circuit with simplified control requirements, is presented. The circuit uses the non-restoring division algorithm which places a restriction on the speed of the circuit. By introducing the concept of bit interleaving, a high speed design can be implemented of the same circuit complexity as an equivalent size multiplier.",

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year = "1997",

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AU - Marnane, W. P.

AU - Bellis, S. J.

AU - Larsson-Edefors, P.

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N2 - A bit-serial/word-parallel divider circuit with simplified control requirements, is presented. The circuit uses the non-restoring division algorithm which places a restriction on the speed of the circuit. By introducing the concept of bit interleaving, a high speed design can be implemented of the same circuit complexity as an equivalent size multiplier.

AB - A bit-serial/word-parallel divider circuit with simplified control requirements, is presented. The circuit uses the non-restoring division algorithm which places a restriction on the speed of the circuit. By introducing the concept of bit interleaving, a high speed design can be implemented of the same circuit complexity as an equivalent size multiplier.

KW - Dividing circuits

KW - VLSI

UR - https://www.scopus.com/pages/publications/0031164005

U2 - 10.1049/el:19970758

DO - 10.1049/el:19970758

M3 - Article

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EP - 1125

JO - Electronics Letters

JF - Electronics Letters

IS - 13

ER -

Bit-serial interleaved high speed division

Abstract

Keywords

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