Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications

A. Vandooren; Z. Wu; A. Khaled; J. Franco; B. Parvais; W. Li; L. Witters; A. Walke; L. Peng; N. Rassoul; P. Matagne; H. Debruyn; G. Jamieson; F. Inoue; K. Devriendt; L. Teugels; N. Heylen; E. Vecchio; T. Zheng; D. Radisic; E. Rosseel; W. Vanherle; A. Hikavyy; B. T. Chan; G. Besnard; W. Schwarzenbach; G. Gaudin; I. Radu; B. Y. Nguyen; N. Waldron; V. De Heyn; S. Demuynck; J. Boemmels; J. Ryckaert; N. Collaert; D. Mocuta

doi:10.23919/VLSIT.2019.8776490

Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic V_th tuning and RF shielding applications

A. Vandooren
, Z. Wu
, A. Khaled
, J. Franco
, B. Parvais
, W. Li
, L. Witters
, A. Walke
, L. Peng
, N. Rassoul
, P. Matagne
, H. Debruyn
, G. Jamieson
, F. Inoue
, K. Devriendt
, L. Teugels
, N. Heylen
, E. Vecchio
, T. Zheng
, D. Radisic

E. Rosseel, W. Vanherle, A. Hikavyy, B. T. Chan, G. Besnard, W. Schwarzenbach, G. Gaudin, I. Radu, B. Y. Nguyen, N. Waldron, V. De Heyn, S. Demuynck, J. Boemmels, J. Ryckaert, N. Collaert, D. Mocuta

Research output: Chapter in Book/Report/Conference proceedings › Chapter › peer-review

Abstract

3D sequential integration is shown to be compatible with a back gate implementation suitable for dynamic V_thtuning of the FDSOI top tier devices. The back gate is inserted seamlessly into the 3D sequential process flow during the top Si layer transfer, providing a close proximity to the top tier device, as well as a uniform and high quality thermal back oxide. A threshold voltage tuning of ∼103mV/V and ∼139mV/V is obtained in p-and nMOS top tier junction-less devices, respectively, over a back gate bias range of +/-2V. BTI reliability measurements show no detrimental impact of the back gate bias. Back-gating can therefore be used to enhance the ION performance with no reliability penalty. The buried metal line is also shown to lower crosstalk by metal shielding insertion between top and bottom tier metal lines, with a reduction larger than 10dB up to 45GHz.

Original language	English
Title of host publication	2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	T56-T57
ISBN (Electronic)	9784863487178
DOIs	https://doi.org/10.23919/VLSIT.2019.8776490
Publication status	Published - Jun 2019
Externally published	Yes
Event	39th Symposium on VLSI Technology, VLSI Technology 2019 - Kyoto, Japan Duration: 9 Jun 2019 → 14 Jun 2019

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2019-June
ISSN (Print)	0743-1562

Conference

Conference	39th Symposium on VLSI Technology, VLSI Technology 2019
Country/Territory	Japan
City	Kyoto
Period	9/06/19 → 14/06/19

Access to Document

10.23919/VLSIT.2019.8776490

Cite this

Vandooren, A., Wu, Z., Khaled, A., Franco, J., Parvais, B., Li, W., Witters, L., Walke, A., Peng, L., Rassoul, N., Matagne, P., Debruyn, H., Jamieson, G., Inoue, F., Devriendt, K., Teugels, L., Heylen, N., Vecchio, E., Zheng, T., ... Mocuta, D. (2019). Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic V_th tuning and RF shielding applications. In 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers (pp. T56-T57). Article 8776490 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2019-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.23919/VLSIT.2019.8776490

Vandooren, A. ; Wu, Z. ; Khaled, A. et al. / Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic V_th tuning and RF shielding applications. 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2019. pp. T56-T57 (Digest of Technical Papers - Symposium on VLSI Technology).

@inbook{6e13f8845358463f93775b899c263c22,

title = "Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications",

abstract = "3D sequential integration is shown to be compatible with a back gate implementation suitable for dynamic Vthtuning of the FDSOI top tier devices. The back gate is inserted seamlessly into the 3D sequential process flow during the top Si layer transfer, providing a close proximity to the top tier device, as well as a uniform and high quality thermal back oxide. A threshold voltage tuning of ∼103mV/V and ∼139mV/V is obtained in p-and nMOS top tier junction-less devices, respectively, over a back gate bias range of +/-2V. BTI reliability measurements show no detrimental impact of the back gate bias. Back-gating can therefore be used to enhance the ION performance with no reliability penalty. The buried metal line is also shown to lower crosstalk by metal shielding insertion between top and bottom tier metal lines, with a reduction larger than 10dB up to 45GHz.",

author = "A. Vandooren and Z. Wu and A. Khaled and J. Franco and B. Parvais and W. Li and L. Witters and A. Walke and L. Peng and N. Rassoul and P. Matagne and H. Debruyn and G. Jamieson and F. Inoue and K. Devriendt and L. Teugels and N. Heylen and E. Vecchio and T. Zheng and D. Radisic and E. Rosseel and W. Vanherle and A. Hikavyy and Chan, \{B. T.\} and G. Besnard and W. Schwarzenbach and G. Gaudin and I. Radu and Nguyen, \{B. Y.\} and N. Waldron and \{De Heyn\}, V. and S. Demuynck and J. Boemmels and J. Ryckaert and N. Collaert and D. Mocuta",

note = "Publisher Copyright: {\textcopyright} 2019 The Japan Society of Applied Physics.; 39th Symposium on VLSI Technology, VLSI Technology 2019 ; Conference date: 09-06-2019 Through 14-06-2019",

year = "2019",

month = jun,

doi = "10.23919/VLSIT.2019.8776490",

language = "English",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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booktitle = "2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers",

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}

Vandooren, A, Wu, Z, Khaled, A, Franco, J, Parvais, B, Li, W, Witters, L, Walke, A, Peng, L, Rassoul, N, Matagne, P, Debruyn, H, Jamieson, G, Inoue, F, Devriendt, K, Teugels, L, Heylen, N, Vecchio, E, Zheng, T, Radisic, D, Rosseel, E, Vanherle, W, Hikavyy, A, Chan, BT, Besnard, G, Schwarzenbach, W, Gaudin, G, Radu, I, Nguyen, BY, Waldron, N, De Heyn, V, Demuynck, S, Boemmels, J, Ryckaert, J, Collaert, N & Mocuta, D 2019, Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic V_th tuning and RF shielding applications. in 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers., 8776490, Digest of Technical Papers - Symposium on VLSI Technology, vol. 2019-June, Institute of Electrical and Electronics Engineers Inc., pp. T56-T57, 39th Symposium on VLSI Technology, VLSI Technology 2019, Kyoto, Japan, 9/06/19. https://doi.org/10.23919/VLSIT.2019.8776490

Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic V_th tuning and RF shielding applications. / Vandooren, A.; Wu, Z.; Khaled, A. et al.
2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2019. p. T56-T57 8776490 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2019-June).

Research output: Chapter in Book/Report/Conference proceedings › Chapter › peer-review

TY - CHAP

T1 - Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic Vth tuning and RF shielding applications

AU - Vandooren, A.

AU - Wu, Z.

AU - Khaled, A.

AU - Franco, J.

AU - Parvais, B.

AU - Li, W.

AU - Witters, L.

AU - Walke, A.

AU - Peng, L.

AU - Rassoul, N.

AU - Matagne, P.

AU - Debruyn, H.

AU - Jamieson, G.

AU - Inoue, F.

AU - Devriendt, K.

AU - Teugels, L.

AU - Heylen, N.

AU - Vecchio, E.

AU - Zheng, T.

AU - Radisic, D.

AU - Rosseel, E.

AU - Vanherle, W.

AU - Hikavyy, A.

AU - Chan, B. T.

AU - Besnard, G.

AU - Schwarzenbach, W.

AU - Gaudin, G.

AU - Radu, I.

AU - Nguyen, B. Y.

AU - Waldron, N.

AU - De Heyn, V.

AU - Demuynck, S.

AU - Boemmels, J.

AU - Ryckaert, J.

AU - Collaert, N.

AU - Mocuta, D.

PY - 2019/6

Y1 - 2019/6

N2 - 3D sequential integration is shown to be compatible with a back gate implementation suitable for dynamic Vthtuning of the FDSOI top tier devices. The back gate is inserted seamlessly into the 3D sequential process flow during the top Si layer transfer, providing a close proximity to the top tier device, as well as a uniform and high quality thermal back oxide. A threshold voltage tuning of ∼103mV/V and ∼139mV/V is obtained in p-and nMOS top tier junction-less devices, respectively, over a back gate bias range of +/-2V. BTI reliability measurements show no detrimental impact of the back gate bias. Back-gating can therefore be used to enhance the ION performance with no reliability penalty. The buried metal line is also shown to lower crosstalk by metal shielding insertion between top and bottom tier metal lines, with a reduction larger than 10dB up to 45GHz.

AB - 3D sequential integration is shown to be compatible with a back gate implementation suitable for dynamic Vthtuning of the FDSOI top tier devices. The back gate is inserted seamlessly into the 3D sequential process flow during the top Si layer transfer, providing a close proximity to the top tier device, as well as a uniform and high quality thermal back oxide. A threshold voltage tuning of ∼103mV/V and ∼139mV/V is obtained in p-and nMOS top tier junction-less devices, respectively, over a back gate bias range of +/-2V. BTI reliability measurements show no detrimental impact of the back gate bias. Back-gating can therefore be used to enhance the ION performance with no reliability penalty. The buried metal line is also shown to lower crosstalk by metal shielding insertion between top and bottom tier metal lines, with a reduction larger than 10dB up to 45GHz.

UR - https://www.scopus.com/pages/publications/85070307264

U2 - 10.23919/VLSIT.2019.8776490

DO - 10.23919/VLSIT.2019.8776490

M3 - Chapter

AN - SCOPUS:85070307264

T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - T56-T57

BT - 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 39th Symposium on VLSI Technology, VLSI Technology 2019

Y2 - 9 June 2019 through 14 June 2019

ER -

Vandooren A, Wu Z, Khaled A, Franco J, Parvais B, Li W et al. Buried metal line compatible with 3D sequential integration for top tier planar devices dynamic V_th tuning and RF shielding applications. In 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2019. p. T56-T57. 8776490. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.23919/VLSIT.2019.8776490