CAD-based analysis of power distribution network for SOC design

Incorporation of power distribution network (PDN) in computer-aided design (CAD) of integrated circuits (ICs) is essential in the recent era. In order to reduce the overall power requirement, the common practice is to reduce the supply voltage. The lowering of supply voltage results in stiffening noise margin and hence increasing the effects of supply voltage fluctuation due to power supply noise. From recent research works, it is also evident that the fluctuation in supply voltage is increasing with scaling down of technology node. A proper estimation of overall power dissipation can only be performed through appropriate and exact parametric extraction of the circuit along with the PDN. Typically there exist many models of voltage fluctuation, which can be utilized to analyze the PDN. In this paper, we propose a new CAD model, which at first estimates a resistance distribution profile of the PDN based on geometric parameters of the chip and electrical parameter of the interconnects (sheet resistance), and then it is mapped with the circuit grid to perform the exact PDN analysis. To the best of our knowledge our proposed model is the first of its kind in regard to PDN analysis. We have chosen one ISCAS 85 benchmark circuit and cryptocores (DES, AES) as SOC applications for our analysis. We have used MATLAB and Mentor Graphics Pyxis tool for our simulation and analysis.