TY - CHAP
T1 - Challenges and opportunities of vertical FET devices using 3D circuit design layouts
AU - Veloso, A.
AU - Huynh-Bao, T.
AU - Rosseel, E.
AU - Paraschiv, V.
AU - Devriendt, K.
AU - Vecchio, E.
AU - Delvaux, C.
AU - Chan, B. T.
AU - Ercken, M.
AU - Tao, Z.
AU - Li, W.
AU - Altamirano-Sánchez, E.
AU - Versluijs, J. J.
AU - Brus, S.
AU - Matagne, P.
AU - Waldron, N.
AU - Ryckaert, J.
AU - Mocuta, D.
AU - Collaert, N.
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016
Y1 - 2016
N2 - We report on vertical nanowire FET devices (VNWFETs) with a gate-all-around (GAA) configuration, which offer promising opportunities to enable further CMOS scaling and increased circuit layout efficiency. They allow up to 30% denser SRAM bitcells with improved read and write stability, smaller minimum operating voltages (Vmin), and lower standby leakage values as compared to cells built with lateral GAA-NWFETs. Furthermore, vertical stacking of these devices also opens the path for SRAM 3D scaling, with a design presented here that can enable, with two levels of transistors in the vertical direction, to reduce by 39% the SRAM area per bit. The two vertically stacked VNWFETs are of the same doping type (n/n or p/p), and a lower complexity of implementation may be possible by taking advantage of the junctionless (JL) concept and its process simplicity, a topic also explored in this work.
AB - We report on vertical nanowire FET devices (VNWFETs) with a gate-all-around (GAA) configuration, which offer promising opportunities to enable further CMOS scaling and increased circuit layout efficiency. They allow up to 30% denser SRAM bitcells with improved read and write stability, smaller minimum operating voltages (Vmin), and lower standby leakage values as compared to cells built with lateral GAA-NWFETs. Furthermore, vertical stacking of these devices also opens the path for SRAM 3D scaling, with a design presented here that can enable, with two levels of transistors in the vertical direction, to reduce by 39% the SRAM area per bit. The two vertically stacked VNWFETs are of the same doping type (n/n or p/p), and a lower complexity of implementation may be possible by taking advantage of the junctionless (JL) concept and its process simplicity, a topic also explored in this work.
KW - CMOS scaling
KW - SRAM
KW - Vertical nanowire FETs
UR - https://www.scopus.com/pages/publications/85011298893
U2 - 10.1109/S3S.2016.7804409
DO - 10.1109/S3S.2016.7804409
M3 - Chapter
AN - SCOPUS:85011298893
T3 - 2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016
BT - 2016 SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2016
Y2 - 10 October 2016 through 13 October 2016
ER -