Challenges on surface conditioning in 3D device architectures: Triple-gate finfets, gate-all-around lateral and vertical nanowire FETs

A. Veloso; V. Paraschiv; E. Vecchio; K. Devriendt; W. Li; E. Simoen; B. T. Chan; Z. Tao; E. Rosseel; R. Loo; A. P. Milenin; B. Kunert; L. Teugels; F. Sebaai; C. Lorant; D. Van Dorp; E. Altamirano-Sánchez; S. Brus; P. Marien; C. Fleischmann; D. Melkonyan; T. Huynh-Bao; G. Eneman; G. Hellings; A. Sibaja-Hernandez; P. Matagne; N. Waldron; D. Mocuta; N. Collaert

doi:10.1149/08002.0003ecst

Challenges on surface conditioning in 3D device architectures: Triple-gate finfets, gate-all-around lateral and vertical nanowire FETs

A. Veloso
, V. Paraschiv
, E. Vecchio
, K. Devriendt
, W. Li
, E. Simoen
, B. T. Chan
, Z. Tao
, E. Rosseel
, R. Loo
, A. P. Milenin
, B. Kunert
, L. Teugels
, F. Sebaai
, C. Lorant
, D. Van Dorp
, E. Altamirano-Sánchez
, S. Brus
, P. Marien
, C. Fleischmann

D. Melkonyan, T. Huynh-Bao, G. Eneman, G. Hellings, A. Sibaja-Hernandez, P. Matagne, N. Waldron, D. Mocuta, N. Collaert

Interuniversitair Micro-Elektronica Centrum

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

Abstract

This work reports on some key integration aspects for 3D devices fabrication, focusing first on the impact of thermal and plasma treatments at gate module for triple-gate finFETs and their ultimate scaling limit: gate-all-around (GAA) nanowire (NW) FETs, which can be implemented in a lateral (with one or more lateral wires vertically stacked) or vertical configuration. The selected doping schemes and gate metals can also be powerful knobs to engineer the interface properties. In addition, specific steps for lateral NWFETs, such as the wires release process, will be addressed here. Vertical NWFETs, corresponding to the move from a 2D to a 3D CMOS layout, have the potential for lower parasitics, reduced power consumption and for enabling smaller, higher performing SRAM bitcells. We will present here alternative, novel approaches for building and characterizing these devices, focusing on channelfirst schemes with improved process control, while tackling critical etch-layout dependences.

Original language	English
Title of host publication	ECS Transactions
Editors	Takeshi Hattori, Anthony J. Muscat, Koichiro Saga, Paul Mertens, Richard E. Novak, Jerzy Ruzyllo
Publisher	Electrochemical Society Inc.
Pages	3-20
Number of pages	18
Edition	2
ISBN (Electronic)	9781607688198
ISBN (Print)	9781623324711
DOIs	https://doi.org/10.1149/08002.0003ecst
Publication status	Published - 2017
Externally published	Yes
Event	15th International Symposium on Semiconductor Cleaning Science and Technology, SCST 2017 - 232nd ECS Meeting - National Harbor, United States Duration: 2 Oct 2017 → 3 Oct 2017

Publication series

Name	ECS Transactions
Number	2
Volume	80
ISSN (Print)	1938-6737
ISSN (Electronic)	1938-5862

Conference

Conference	15th International Symposium on Semiconductor Cleaning Science and Technology, SCST 2017 - 232nd ECS Meeting
Country/Territory	United States
City	National Harbor
Period	2/10/17 → 3/10/17

Access to Document

10.1149/08002.0003ecst

Cite this

Veloso, A., Paraschiv, V., Vecchio, E., Devriendt, K., Li, W., Simoen, E., Chan, B. T., Tao, Z., Rosseel, E., Loo, R., Milenin, A. P., Kunert, B., Teugels, L., Sebaai, F., Lorant, C., Van Dorp, D., Altamirano-Sánchez, E., Brus, S., Marien, P., ... Collaert, N. (2017). Challenges on surface conditioning in 3D device architectures: Triple-gate finfets, gate-all-around lateral and vertical nanowire FETs. In T. Hattori, A. J. Muscat, K. Saga, P. Mertens, R. E. Novak, & J. Ruzyllo (Eds.), ECS Transactions (2 ed., pp. 3-20). (ECS Transactions; Vol. 80, No. 2). Electrochemical Society Inc.. https://doi.org/10.1149/08002.0003ecst

Veloso, A. ; Paraschiv, V. ; Vecchio, E. et al. / Challenges on surface conditioning in 3D device architectures : Triple-gate finfets, gate-all-around lateral and vertical nanowire FETs. ECS Transactions. editor / Takeshi Hattori ; Anthony J. Muscat ; Koichiro Saga ; Paul Mertens ; Richard E. Novak ; Jerzy Ruzyllo. 2. ed. Electrochemical Society Inc., 2017. pp. 3-20 (ECS Transactions; 2).

@inproceedings{0c9f1567336e4607948ed428b2d22d9a,

title = "Challenges on surface conditioning in 3D device architectures: Triple-gate finfets, gate-all-around lateral and vertical nanowire FETs",

abstract = "This work reports on some key integration aspects for 3D devices fabrication, focusing first on the impact of thermal and plasma treatments at gate module for triple-gate finFETs and their ultimate scaling limit: gate-all-around (GAA) nanowire (NW) FETs, which can be implemented in a lateral (with one or more lateral wires vertically stacked) or vertical configuration. The selected doping schemes and gate metals can also be powerful knobs to engineer the interface properties. In addition, specific steps for lateral NWFETs, such as the wires release process, will be addressed here. Vertical NWFETs, corresponding to the move from a 2D to a 3D CMOS layout, have the potential for lower parasitics, reduced power consumption and for enabling smaller, higher performing SRAM bitcells. We will present here alternative, novel approaches for building and characterizing these devices, focusing on channelfirst schemes with improved process control, while tackling critical etch-layout dependences.",

author = "A. Veloso and V. Paraschiv and E. Vecchio and K. Devriendt and W. Li and E. Simoen and Chan, \{B. T.\} and Z. Tao and E. Rosseel and R. Loo and Milenin, \{A. P.\} and B. Kunert and L. Teugels and F. Sebaai and C. Lorant and \{Van Dorp\}, D. and E. Altamirano-S{\'a}nchez and S. Brus and P. Marien and C. Fleischmann and D. Melkonyan and T. Huynh-Bao and G. Eneman and G. Hellings and A. Sibaja-Hernandez and P. Matagne and N. Waldron and D. Mocuta and N. Collaert",

note = "Publisher Copyright: {\textcopyright} The Electrochemical Society.; 15th International Symposium on Semiconductor Cleaning Science and Technology, SCST 2017 - 232nd ECS Meeting ; Conference date: 02-10-2017 Through 03-10-2017",

year = "2017",

doi = "10.1149/08002.0003ecst",

language = "English",

isbn = "9781623324711",

series = "ECS Transactions",

publisher = "Electrochemical Society Inc.",

number = "2",

pages = "3--20",

editor = "Takeshi Hattori and Muscat, \{Anthony J.\} and Koichiro Saga and Paul Mertens and Novak, \{Richard E.\} and Jerzy Ruzyllo",

booktitle = "ECS Transactions",

address = "United States",

edition = "2",

}

Veloso, A, Paraschiv, V, Vecchio, E, Devriendt, K, Li, W, Simoen, E, Chan, BT, Tao, Z, Rosseel, E, Loo, R, Milenin, AP, Kunert, B, Teugels, L, Sebaai, F, Lorant, C, Van Dorp, D, Altamirano-Sánchez, E, Brus, S, Marien, P, Fleischmann, C, Melkonyan, D, Huynh-Bao, T, Eneman, G, Hellings, G, Sibaja-Hernandez, A, Matagne, P, Waldron, N, Mocuta, D & Collaert, N 2017, Challenges on surface conditioning in 3D device architectures: Triple-gate finfets, gate-all-around lateral and vertical nanowire FETs. in T Hattori, AJ Muscat, K Saga, P Mertens, RE Novak & J Ruzyllo (eds), ECS Transactions. 2 edn, ECS Transactions, no. 2, vol. 80, Electrochemical Society Inc., pp. 3-20, 15th International Symposium on Semiconductor Cleaning Science and Technology, SCST 2017 - 232nd ECS Meeting, National Harbor, United States, 2/10/17. https://doi.org/10.1149/08002.0003ecst

Challenges on surface conditioning in 3D device architectures: Triple-gate finfets, gate-all-around lateral and vertical nanowire FETs. / Veloso, A.; Paraschiv, V.; Vecchio, E. et al.
ECS Transactions. ed. / Takeshi Hattori; Anthony J. Muscat; Koichiro Saga; Paul Mertens; Richard E. Novak; Jerzy Ruzyllo. 2. ed. Electrochemical Society Inc., 2017. p. 3-20 (ECS Transactions; Vol. 80, No. 2).

Research output: Chapter in Book/Report/Conference proceedings › Conference proceeding › peer-review

TY - GEN

T1 - Challenges on surface conditioning in 3D device architectures

T2 - 15th International Symposium on Semiconductor Cleaning Science and Technology, SCST 2017 - 232nd ECS Meeting

AU - Veloso, A.

AU - Paraschiv, V.

AU - Vecchio, E.

AU - Devriendt, K.

AU - Li, W.

AU - Simoen, E.

AU - Chan, B. T.

AU - Tao, Z.

AU - Rosseel, E.

AU - Loo, R.

AU - Milenin, A. P.

AU - Kunert, B.

AU - Teugels, L.

AU - Sebaai, F.

AU - Lorant, C.

AU - Van Dorp, D.

AU - Altamirano-Sánchez, E.

AU - Brus, S.

AU - Marien, P.

AU - Fleischmann, C.

AU - Melkonyan, D.

AU - Huynh-Bao, T.

AU - Eneman, G.

AU - Hellings, G.

AU - Sibaja-Hernandez, A.

AU - Matagne, P.

AU - Waldron, N.

AU - Mocuta, D.

AU - Collaert, N.

PY - 2017

Y1 - 2017

N2 - This work reports on some key integration aspects for 3D devices fabrication, focusing first on the impact of thermal and plasma treatments at gate module for triple-gate finFETs and their ultimate scaling limit: gate-all-around (GAA) nanowire (NW) FETs, which can be implemented in a lateral (with one or more lateral wires vertically stacked) or vertical configuration. The selected doping schemes and gate metals can also be powerful knobs to engineer the interface properties. In addition, specific steps for lateral NWFETs, such as the wires release process, will be addressed here. Vertical NWFETs, corresponding to the move from a 2D to a 3D CMOS layout, have the potential for lower parasitics, reduced power consumption and for enabling smaller, higher performing SRAM bitcells. We will present here alternative, novel approaches for building and characterizing these devices, focusing on channelfirst schemes with improved process control, while tackling critical etch-layout dependences.

AB - This work reports on some key integration aspects for 3D devices fabrication, focusing first on the impact of thermal and plasma treatments at gate module for triple-gate finFETs and their ultimate scaling limit: gate-all-around (GAA) nanowire (NW) FETs, which can be implemented in a lateral (with one or more lateral wires vertically stacked) or vertical configuration. The selected doping schemes and gate metals can also be powerful knobs to engineer the interface properties. In addition, specific steps for lateral NWFETs, such as the wires release process, will be addressed here. Vertical NWFETs, corresponding to the move from a 2D to a 3D CMOS layout, have the potential for lower parasitics, reduced power consumption and for enabling smaller, higher performing SRAM bitcells. We will present here alternative, novel approaches for building and characterizing these devices, focusing on channelfirst schemes with improved process control, while tackling critical etch-layout dependences.

UR - https://www.scopus.com/pages/publications/85050033597

U2 - 10.1149/08002.0003ecst

DO - 10.1149/08002.0003ecst

M3 - Conference proceeding

AN - SCOPUS:85050033597

SN - 9781623324711

T3 - ECS Transactions

SP - 3

EP - 20

BT - ECS Transactions

A2 - Hattori, Takeshi

A2 - Muscat, Anthony J.

A2 - Saga, Koichiro

A2 - Mertens, Paul

A2 - Novak, Richard E.

A2 - Ruzyllo, Jerzy

PB - Electrochemical Society Inc.

Y2 - 2 October 2017 through 3 October 2017

ER -

Veloso A, Paraschiv V, Vecchio E, Devriendt K, Li W, Simoen E et al. Challenges on surface conditioning in 3D device architectures: Triple-gate finfets, gate-all-around lateral and vertical nanowire FETs. In Hattori T, Muscat AJ, Saga K, Mertens P, Novak RE, Ruzyllo J, editors, ECS Transactions. 2 ed. Electrochemical Society Inc. 2017. p. 3-20. (ECS Transactions; 2). doi: 10.1149/08002.0003ecst

Challenges on surface conditioning in 3D device architectures: Triple-gate finfets, gate-all-around lateral and vertical nanowire FETs

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