Characterization of oxide defects in InGaAs MOS gate stacks for high-mobility n-channel MOSFETs (invited)

J. Franco; V. Putcha; A. Vais; S. Sioncke; N. Waldron; D. Zhou; G. Rzepa; Ph J. Roussel; G. Groeseneken; M. Heyns; N. Collaert; D. Linten; T. Grasser; B. Kaczer

doi:10.1109/IEDM.2017.8268347

Characterization of oxide defects in InGaAs MOS gate stacks for high-mobility n-channel MOSFETs (invited)

J. Franco
, V. Putcha
, A. Vais
, S. Sioncke
, N. Waldron
, D. Zhou
, G. Rzepa
, Ph J. Roussel
, G. Groeseneken
, M. Heyns
, N. Collaert
, D. Linten
, T. Grasser
, B. Kaczer

Research output: Chapter in Book/Report/Conference proceedings › Chapter › peer-review

Abstract

We review our recent studies of oxide traps in InGaAs MOS gate stacks for novel high-mobility n-channel MOSFETs. We discuss and correlate various trap characterization techniques such as Bias Temperature Instability, defect Capture-Emission-Time maps (applied here to InGaAs devices), Random Telegraph Noise, hysteresis traces, multi-frequency C-V dispersion, all performed on a variety of device test vehicles (capacitors, planar MOSFETs, finFETs, nanowires). Finally we demonstrate guidelines for developing sufficiently reliable IIIV gate stacks.

Original language	English
Title of host publication	2017 IEEE International Electron Devices Meeting, IEDM 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	7.5.1-7.5.4
ISBN (Electronic)	9781538635599
DOIs	https://doi.org/10.1109/IEDM.2017.8268347
Publication status	Published - 23 Jan 2018
Externally published	Yes
Event	63rd IEEE International Electron Devices Meeting, IEDM 2017 - San Francisco, United States Duration: 2 Dec 2017 → 6 Dec 2017

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)	0163-1918

Conference

Conference	63rd IEEE International Electron Devices Meeting, IEDM 2017
Country/Territory	United States
City	San Francisco
Period	2/12/17 → 6/12/17

Access to Document

10.1109/IEDM.2017.8268347

Cite this

Franco, J., Putcha, V., Vais, A., Sioncke, S., Waldron, N., Zhou, D., Rzepa, G., Roussel, P. J., Groeseneken, G., Heyns, M., Collaert, N., Linten, D., Grasser, T., & Kaczer, B. (2018). Characterization of oxide defects in InGaAs MOS gate stacks for high-mobility n-channel MOSFETs (invited). In 2017 IEEE International Electron Devices Meeting, IEDM 2017 (pp. 7.5.1-7.5.4). (Technical Digest - International Electron Devices Meeting, IEDM). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2017.8268347

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title = "Characterization of oxide defects in InGaAs MOS gate stacks for high-mobility n-channel MOSFETs (invited)",

abstract = "We review our recent studies of oxide traps in InGaAs MOS gate stacks for novel high-mobility n-channel MOSFETs. We discuss and correlate various trap characterization techniques such as Bias Temperature Instability, defect Capture-Emission-Time maps (applied here to InGaAs devices), Random Telegraph Noise, hysteresis traces, multi-frequency C-V dispersion, all performed on a variety of device test vehicles (capacitors, planar MOSFETs, finFETs, nanowires). Finally we demonstrate guidelines for developing sufficiently reliable IIIV gate stacks.",

author = "J. Franco and V. Putcha and A. Vais and S. Sioncke and N. Waldron and D. Zhou and G. Rzepa and Roussel, \{Ph J.\} and G. Groeseneken and M. Heyns and N. Collaert and D. Linten and T. Grasser and B. Kaczer",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 63rd IEEE International Electron Devices Meeting, IEDM 2017 ; Conference date: 02-12-2017 Through 06-12-2017",

year = "2018",

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doi = "10.1109/IEDM.2017.8268347",

language = "English",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "7.5.1--7.5.4",

booktitle = "2017 IEEE International Electron Devices Meeting, IEDM 2017",

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Franco, J, Putcha, V, Vais, A, Sioncke, S, Waldron, N, Zhou, D, Rzepa, G, Roussel, PJ, Groeseneken, G, Heyns, M, Collaert, N, Linten, D, Grasser, T & Kaczer, B 2018, Characterization of oxide defects in InGaAs MOS gate stacks for high-mobility n-channel MOSFETs (invited). in 2017 IEEE International Electron Devices Meeting, IEDM 2017. Technical Digest - International Electron Devices Meeting, IEDM, Institute of Electrical and Electronics Engineers Inc., pp. 7.5.1-7.5.4, 63rd IEEE International Electron Devices Meeting, IEDM 2017, San Francisco, United States, 2/12/17. https://doi.org/10.1109/IEDM.2017.8268347

Characterization of oxide defects in InGaAs MOS gate stacks for high-mobility n-channel MOSFETs (invited). / Franco, J.; Putcha, V.; Vais, A. et al.
2017 IEEE International Electron Devices Meeting, IEDM 2017. Institute of Electrical and Electronics Engineers Inc., 2018. p. 7.5.1-7.5.4 (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceedings › Chapter › peer-review

TY - CHAP

T1 - Characterization of oxide defects in InGaAs MOS gate stacks for high-mobility n-channel MOSFETs (invited)

AU - Franco, J.

AU - Putcha, V.

AU - Vais, A.

AU - Sioncke, S.

AU - Waldron, N.

AU - Zhou, D.

AU - Rzepa, G.

AU - Roussel, Ph J.

AU - Groeseneken, G.

AU - Heyns, M.

AU - Collaert, N.

AU - Linten, D.

AU - Grasser, T.

AU - Kaczer, B.

PY - 2018/1/23

Y1 - 2018/1/23

N2 - We review our recent studies of oxide traps in InGaAs MOS gate stacks for novel high-mobility n-channel MOSFETs. We discuss and correlate various trap characterization techniques such as Bias Temperature Instability, defect Capture-Emission-Time maps (applied here to InGaAs devices), Random Telegraph Noise, hysteresis traces, multi-frequency C-V dispersion, all performed on a variety of device test vehicles (capacitors, planar MOSFETs, finFETs, nanowires). Finally we demonstrate guidelines for developing sufficiently reliable IIIV gate stacks.

AB - We review our recent studies of oxide traps in InGaAs MOS gate stacks for novel high-mobility n-channel MOSFETs. We discuss and correlate various trap characterization techniques such as Bias Temperature Instability, defect Capture-Emission-Time maps (applied here to InGaAs devices), Random Telegraph Noise, hysteresis traces, multi-frequency C-V dispersion, all performed on a variety of device test vehicles (capacitors, planar MOSFETs, finFETs, nanowires). Finally we demonstrate guidelines for developing sufficiently reliable IIIV gate stacks.

UR - https://www.scopus.com/pages/publications/85045188228

U2 - 10.1109/IEDM.2017.8268347

DO - 10.1109/IEDM.2017.8268347

M3 - Chapter

AN - SCOPUS:85045188228

T3 - Technical Digest - International Electron Devices Meeting, IEDM

SP - 7.5.1-7.5.4

BT - 2017 IEEE International Electron Devices Meeting, IEDM 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 63rd IEEE International Electron Devices Meeting, IEDM 2017

Y2 - 2 December 2017 through 6 December 2017

ER -

Franco J, Putcha V, Vais A, Sioncke S, Waldron N, Zhou D et al. Characterization of oxide defects in InGaAs MOS gate stacks for high-mobility n-channel MOSFETs (invited). In 2017 IEEE International Electron Devices Meeting, IEDM 2017. Institute of Electrical and Electronics Engineers Inc. 2018. p. 7.5.1-7.5.4. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM.2017.8268347

Characterization of oxide defects in InGaAs MOS gate stacks for high-mobility n-channel MOSFETs (invited)

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