CMOS device optimization for mixed-signal technologies

  • P. A. Stolk
  • , H. P. Tuinhout
  • , R. Duffy
  • , E. Augendre
  • , L. P. Bellefroid
  • , M. J.B. Bolt
  • , J. Croon
  • , C. J.J. Dachs
  • , F. R.J. Huisman
  • , A. J. Moonen
  • , Y. V. Ponomarev
  • , R. F.M. Roes
  • , M. Da Rold
  • , E. Seevinck
  • , K. N. Sreerambhatla
  • , R. Surdeanu
  • , R. M.D.A. Velghe
  • , M. Vertregt
  • , M. N. Webster
  • , N. K.J. Van Winkelhoff
  • A. T.A. Zegers-Van Duijnhoven

Research output: Contribution to journalArticlepeer-review

Abstract

This paper studies the suitability of CMOS device technology for mixed-signal applications. The currently proposed scaling scenario's for CMOS technologies lead to strong degradation of analog transistor performance. As a result, the combined optimization of digital and analog devices for system-on-a-chip applications will require increasingly elaborate process modifications. New device solutions such as metal gate integration and asymmetric (source-side-only) workfunction modification offer process options for future mixed-signal CMOS applications.

Original languageEnglish
Pages (from-to)215-218
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
DOIs
Publication statusPublished - 2001
Externally publishedYes

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