Co-implantation for 45 nm PMOS and NMOS source-drain extension formation: Device characterisation down to 30 nm physical gate length

We have optimised co-implantation schemes for NMOS and PMOS USJ formation down to 30 nm physical gate length. These schemes included Ge or Si pre-amorphisation steps, followed by C and/or F and dopant implants of P and B for NMOS and PMOS, respectively. Junction depth and sheet resistance optimisation on blanket wafers was complemented with electrical device data. Blanket wafer results show junction depuis as low as 15 nm at 5×10 ¹⁸ cm^-3, abruptness around 2.5 nm/decade and Rs in the 400-600 Ω/□ range. Device data show very good Vt roll-off behaviour down to 30 nm physical gate length, and good lon/Ioff curves. Leakage currents are higher than in reference devices, but within acceptable limits for general purpose applications. The leakage has been found to be a very sensitive function of dopant and non-dopant species placement. The main cause for the I _off-leak is trap-assisted tunnelling through C clustering with residual damage in the depletion layer, rather than band-to-band tunnelling. Optimisation of extension implant conditions as well as halo and spacer may improve leakage characteristics and device performance further.