Compiling regular arrays onto FPGAs

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Abstract

Many DSP functions can be implemented as arrays of simple Processing Elements (PEs) connected to their nearest neighbours in a regular manner. Field Programmable Gate Arrays consist of an array of user-configurable logic blocks and a matrix of user configurable interconnection between the logic blocks. Thus FPGAs are prime candidates for implementing regular arrays. In this paper we present FPGA Regular Array Description Language (FRADL) which will map the regular array into a FPGA.

Original languageEnglish
Title of host publicationField-Programmable Logic and Applications - 5th International Workshop, FPL 1995, Proceedings
EditorsWill Moore, Wayne Luk
PublisherSpringer Verlag
Pages178-187
Number of pages10
ISBN (Print)3540602941, 9783540602941
DOIs
Publication statusPublished - 1995
Event5th International Workshop on Field-Programmable Logic and Applications, FPL 1995 - Oxford, United Kingdom
Duration: 29 Aug 19951 Sep 1995

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume975
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Conference

Conference5th International Workshop on Field-Programmable Logic and Applications, FPL 1995
Country/TerritoryUnited Kingdom
CityOxford
Period29/08/951/09/95

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