Correcting ADC jitter using DPLL timing error signal

In this paper we consider systems comprising an ADC clocked by TDC-based DPLL and we develop an all-digital method to generate real-time estimates of the instantaneous timing jitter and methods for the post-correction / interpolation of the ADC outputs so as to mitigate the impact of the DPLL jitter. This enables the DPLL jitter specification to be relaxed facilitation a significant overall system power saving. We propose an off-line Least-square estimation to design an FIR filter for use at run-time to generate instantaneous jitter estimates. We also provide details of the possible first and second order post-ADC correction algorithms. The effectiveness of our system is demonstrated through simulation to achieve overall performance measured by SNR for a specific realistic system setup. Based on these simulations, we propose a final architecture that has an SNR improvement of up to 33 dB across the target operation frequency range when compared to uncorrected ADC outputs.