Correlation of TMD Defects with Device Performance in Ultra-Scaled Channels: Theoretical Insights and Experimental Observations

In order to adopt novel 2D transition metal dichalcogenide (TMD) materials into new applications, such as highly scaled CMOS, better understanding of TMD defectivity is needed. Here, we present a comprehensive analysis of the effects of one-dimensional (1D) and zero-dimensional (0D) defects in monolayer (ML) MoS_2. We specifically examine two prevalent types of grain boundaries (GBs), namely 4|4E and 4|4P, as well as molybdenum (Mo) and sulfur (S) vacancies. While it is clear that TMD defects pose a serious concern for device variability, our results reveal that the impact of GBs on device performance actually depends on a number of factors: i) GB type, ii) device polarity, iii) position of GB, and iv) channel length. In some instances, the GB may even have very little impact on device performance. Further, we correlate linear channel defects to device performance through ALD decoration of linear defects in large-area grown ML MoS₂ devices, which consistently aligns with our theoretical predictions.