Cost effective FPGA probabilistic fault emulation

This paper presents a cost effective FPGA fault emulation technique for probabilistic errors. The problem it addresses is how to efficiently inject faults in many locations within a circuit under test. For this purpose, the emulated fault injection (EFI) components proposed are a trade-off between the desire for speed/performance and the inherent physical device limitations of the FPGA. The proposed method also allows exploring the best option for this trade-off with minimal effort. The proposed solution allows enough flexibility to be able to deal with the different EFI architectures selectable by minor code intervention. An analysis of the overhead introduced by EFI components when varying the number of fault locations has been provided. Furthermore, this paper presents a case study of two ISCAS benchmark circuits in order to test our methodologies and to highlight the differences for combinatorial and a sequential circuits. It is shown that the number of fault locations can be increased more than 20 times with similar overhead than other state of the art methods reported in the literature.